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The present work aims to explain how the nonlinear average model can be used in power electronic integration design as a behavioral model.

The nonlinear average model is used in power electronic integration design as a behavioral model, where it is applied to a voltage source inverter based on IGBTs. This model was chosen because it takes into account the nonlinearity of the power semiconductor components and the wiring circuit effects, which can be formalized by the virtual delay concept. In addition, the nonlinear average model cannot distinguish between slow and quick variables and this is an important feature of the model convergence.

The paper studies extensively the construction of the nonlinear average model algorithm theoretically. Detailed explanations of the application of this model to voltage source inverter design are provided. The study demonstrates how this model illustrates the effect of the nonlinearity of the power semiconductor components' characteristics on dynamic electrical quantities. It also predicts the effects due to wiring in the inverter circuit.

More simulations and experimental analysis are still necessary to improve the model's accuracy, by using other static characteristic approaches, and to validate the applicability of the model to different converter topologies.

The paper formulates a simple nonlinear average model algorithm, discussing each step. This model was described by VHDL‐AMS. On the one hand, it will assist theoretical and practical research on different topologies of power electronic converters, particularly in power integration systems design such as the integrated power electronics modules (IPEM). On the other hand, it will give designers a more precise behavioral model with a simpler design process.

The nonlinear average model used in power electronic integration design as behavioral model is a novel approach. This model reduces computational costs significantly, takes physical effects into account and is easy to implement.

Aim of the present monograph is the economic analysis of the role of MNEs regarding globalisation and digital economy and in parallel there is a reference and examination of some legal aspects concerning MNEs, cyberspace and e‐commerce as the means of expression of the digital economy. The whole effort of the author is focused on the examination of various aspects of MNEs and their impact upon globalisation and vice versa and how and if we are moving towards a global digital economy.

Briefly reviews previous literature by the author before presenting an original 12 step system integration protocol designed to ensure the success of companies or countries in their efforts to develop and market new products. Looks at the issues from different strategic levels such as corporate, international, military and economic. Presents 31 case studies, including the success of Japan in microchips to the failure of Xerox to sell its invention of the Alto personal computer 3 years before Apple: from the success in DNA and Superconductor research to the success of Sunbeam in inventing and marketing food processors: and from the daring invention and production of atomic energy for survival to the successes of sewing machine inventor Howe in co‐operating on patents to compete in markets. Includes 306 questions and answers in order to qualify concepts introduced.

Discusses the 27 papers in ISEF 1999 Proceedings on the subject of electromagnetisms. States the groups of papers cover such subjects within the discipline as: induction machines; reluctance motors; PM motors; transformers and reactors; and special problems and applications. Debates all of these in great detail and itemizes each with greater in‐depth discussion of the various technical applications and areas. Concludes that the recommendations made should be adhered to.

Compiled by K.G.B. Bakewell covering the following journals published by MCB University Press: Facilities Volumes 8‐18; Journal of Property Investment & Finance Volumes 8‐18; Property Management Volumes 8‐18; Structural Survey Volumes 8‐18.

Index by subjects, compiled by K.G.B. Bakewell covering the following journals: Facilities Volumes 8‐18; Journal of Property Investment & Finance Volumes 8‐18; Property Management Volumes 8‐18; Structural Survey Volumes 8‐18.

Compiled by K.G.B. Bakewell covering the following journals published by MCB University Press: Facilities Volumes 8‐18; Journal of Property Investment & Finance Volumes 8‐18; Property Management Volumes 8‐18; Structural Survey Volumes 8‐18.

Compiled by K.G.B. Bakewell covering the following journals published by MCB University Press: Facilities Volumes 8‐18; Journal of Property Investment & Finance Volumes 8‐18; Property Management Volumes 8‐18; Structural Survey Volumes 8‐18.

The purpose of this paper is to present a hybrid manufacturing system that integrates stereolithography (SL) and direct print (DP) technologies to fabricate three‐dimensional (3D) structures with embedded electronic circuits. A detailed process was developed that enables fabrication of monolithic 3D packages with electronics without removal from the hybrid SL/DP machine during the process. Successful devices are demonstrated consisting of simple 555 timer circuits designed and fabricated in 2D (single layer of routing) and 3D (multiple layers of routing and component placement).

A hybrid SL/DP system was designed and developed using a 3D Systems SL 250/50 machine and an nScrypt micro‐dispensing pump integrated within the SL machine through orthogonally‐aligned linear translation stages. A corresponding manufacturing process was also developed using this system to fabricate 2D and 3D monolithic structures with embedded electronic circuits. The process involved part design, process planning, integrated manufacturing (including multiple starts and stops of both SL and DP and multiple intermediate processes), and post‐processing. SL provided substrate/mechanical structure manufacturing while interconnections were achieved using DP of conductive inks. Simple functional demonstrations involving 2D and 3D circuit designs were accomplished.

The 3D micro‐dispensing DP system provided control over conductive trace deposition and combined with the manufacturing flexibility of the SL machine enabled the fabrication of monolithic 3D electronic structures. To fabricate a 3D electronic device within the hybrid SL/DP machine, a process was developed that required multiple starts and stops of the SL process, removal of uncured resin from the SL substrate, insertion of active and passive electronic components, and DP and laser curing of the conductive traces. Using this process, the hybrid SL/DP technology was capable of successfully fabricating, without removal from the machine during fabrication, functional 2D and 3D 555 timer circuits packaged within SL substrates.

Results indicated that fabrication of 3D embedded electronic systems is possible using the hybrid SL/DP machine. A complete manufacturing process was developed to fabricate complex, monolithic 3D structures with electronics in a single set‐up, advancing the capabilities of additive manufacturing (AM) technologies. Although the process does not require removal of the structure from the machine during fabrication, many of the current sub‐processes are manual. As a result, further research and development on automation and optimization of many of the sub‐processes are required to enhance the overall manufacturing process.

A new methodology is presented for manufacturing non‐traditional electronic systems in arbitrary form, while achieving miniaturization and enabling rugged structure. Advanced applications are demonstrated using a semi‐automated approach to SL/DP integration. Opportunities exist to fully automate the hybrid SL/DP machine and optimize the manufacturing process for enhancing the commercial appeal for fabricating complex systems.

This work broadly demonstrates what can be achieved by integrating multiple AM technologies together for fabricating unique devices and more specifically demonstrates a hybrid SL/DP machine that can produce 3D monolithic structures with embedded electronics and printed interconnects.

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

The paper's findings will be very useful to the electronic industry.