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Several ultra-low power and gigahertz current-starved voltage-controlled oscillator (CSVCO) circuits have been proposed and compared here. The presented structures are based on the three-stage hybrid circuit of the carbon nanotube field-effect transistors (CNTFETs) and low-power MOSFETs. The topologies exploit modified and compensated Schmitt trigger comparator parts to demonstrate better consumption power and frequency characteristics. The basic idea in the presented topologies is to compensate the Schmitt trigger comparator part of the basic CSVCO for achieving faster carrier mobility of the holes, reducing transistor leakage current and eliminating dummy transistors.

This study aims to propose and compare three different comparator-based VCOs that have been implemented using the CNTFETs. The considered circuits are shown to be capable of delivering the maximum 35 tuning frequency in the order of 1 GHz to 5 GHz. A major power thirsty part of the high-frequency ring VCOs is the Schmitt trigger stage. Here, several fast and low-power Schmitt trigger topologies are exploited to mitigate the dissipation power and enhance the oscillation frequency.

As a result of proposed modifications, more than one order of magnitude mitigation in the VCO power consumption with respect to the previously presented three-stage CSVCO is reported here. Thus, a VCO dissipation power of 3.5 µW at the frequency of 1.1 GHz and the tuning range of 26 per cent is observed for the well-established 32 nm technology and the supply voltage of 1 V. Such a low dissipation power is obtained around the operating frequency of the battery-powered cellular phones. In addition, using the p-carrier mobility compensation and enhancing the rise time of the Schmitt trigger part of the CSVCO, a maximum of 2.38 times higher oscillation frequency and 72 per cent wider tuning range with respect to Rahane and Kureshi (2017) are observed. Simultaneously, this topology exhibits an average of 20 per cent reduction in the power consumption.

Several new VCO topologies are presented here, and it is shown that they can significantly enhance the power dissipation of the GHz CSVCOs.

Delay and power dissipation are the two major design constraints in very large scale integration (VLSI) circuits. These arise due to millions of active devices and interconnections connecting this gigantic number of devices on the chip. Important technique of repeater insertion in long interconnections to reduce delay in VLSI circuits has been reported during the last two decades. This paper deals with delay, power dissipation and the role of voltage‐scaling in repeaters loaded long interconnects in VLSI circuits for low power environment.

Trade off between delay and power dissipation in repeaters inserted long interconnects has been reviewed here with a bibliographic survey. SPICE simulations have been used to validate the findings.

Optimum number of uniform sized CMOS repeaters inserted in long interconnects, lead to delay minimization. Voltage‐scaling is highly effective in reduction of power dissipation in repeaters loaded long interconnects. The new finding given here is that optimum number of repeaters required for delay minimization decreases with voltage‐scaling. This leads to area and further power saving.

The bibliographic survey needs to be revised in future, taking the various other aspects of VLSI interconnects viz. noise, cross talk extra into account.

The paper is of high significance in VLSI design and low‐power high‐speed applications. It is also valuable for new researchers in this emerging field.

This paper aims to obtain the optimal wire sizing of buffered global interconnects and to investigate the impact of weight factor on the optimized system performance for various technology nodes.

The width and spacing of interconnects are optimized under two scenarios, and corresponding optimum line width is determined by minimizing the value of power‐delay product which is defined as a figure of merit (FOM). Based on the results, the impact of weight factor on the optimized system performance, such as delay and power dissipation per unit length, is analyzed for various technology nodes.

The analytical expressions of the optimum width are derived under two scenarios. Better FOMs can be achieved for the S=W scenario, but the wireability of the chip degrades considerably. The optimized delay increases with the increasing of weight factor, while the optimized power dissipation decreases with it. For a given weight factor, smaller latency and less power dissipation can be achieved for the S=W case.

The analytical expressions of the optimum width of interconnects are given, and a comprehensive study of the impact of weight factor on the optimized results under two scenarios is presented.

The purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).

In the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.

The design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.

The study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

The performance of a high‐speed chip is highly dependent on the interconnects, which connect different macro cells within a VLSI chip. Delay, power dissipation and cross‐talk are the major design constraints for high performance VLSI interconnects. The importance of on‐chip inductance is continuously increasing with higher clock frequency, faster on‐chip rise time, wider wires, ever‐growing length of interconnects and introduction of new materials for low resistance interconnects. In the current scenario, interconnect is modeled as an RLC transmission line. Interconnect width optimization plays an important role in deciding transition delay and power dissipation. This paper aims to optimize interconnect width for a matched condition to reduce power and delay parameters.

Width optimization is done for two sets of interconnect terminating conditions, namely active gate and passive capacitance. SPICE simulations have been used to validate the findings.

For a driver interconnect load model terminated by an active gate load, a trade‐off exists between short circuit and dynamic power in inductive interconnects, since with wider lines dynamic power increases, but short circuit power of the load gate decreases due to reduced transient delay. Whereas, for a line terminated by a capacitor, such trade‐off does not exist. Many of the previous researches have modeled the active gate load at the terminating end by its input parasitic gate capacitance.

This paper shows that such modeling leads to inaccuracy in estimation of power, and therefore non‐optimal width selection, especially for large fan‐out conditions.

The finding is that the impedance matching between transmission line at driver and load ends plays an important role in estimation of overall power dissipation and transition delay of a VLSI circuit.

The purpose of this paper is to investigate the thermal behaviour of thin- and thick-film resistor with different dimensions and contacts embedded into printed circuit board (PCB) and compare them to the similar constructions of discrete chip resistors assembled to standard PCBs.

In investigations the thin- and thick-film embedded resistors with the bar form in different dimensions and configurations of contacts as well as rectangular chip resistors in package 0603 and 0402 were used. In tests were carried out the measurements of dissipated power in temperature of resistor about 40°C, 70°C and 155°C. The power dissipation was calculated as a multiplying of electrical current flowing through the resistor with voltage across the resistor. The dissipation of heat generated by electrical current flowing through resistors was examined by means of the FLIR A320 thermographic camera with lens Closeup×2 and the power source.

The results show that, in case of chip resistors, the intensity of heat radiation strongly depends on dimensions of copper contact lands and also depends on the dimensions of the resistor. In case of embedded resistors, with comparable dimensions to chip resistors, they have lower ability to power dissipation, as well as the copper contact lands dimensions have lower influence. The thermal radiation through resin material is not as effective as it is in case of resistors assembled on PCB. However, the embedded thick-film resistors, especially made of paste Minico M2010, have already the similar parameters to 0402 chip resistors.

Research shows that embedded resistors can be used interchangeably with SMD resistors it allows to open up space on the surface of PCB, but it should be taken into account the lower energy dissipation capabilities. It is suggested that further studies are necessary for accurately determining the thermal effects and investigate the structures of embedded passive components that allow for better heat management.

Thermal stability of embedded resistors during operation is a critical factor of success of embedded resistor technology. The way of power dissipation and heat resistance are one of the important operating parameters of these components. The results provide information about the power and the energy dissipation of embedded thin- and thick-film resistors compared to the standard surface mount technology.

The purpose of this paper is to experimentally and theoretically investigate slippers, which have an important role on power dissipation in the swash plate axial piston pumps.

The slipper geometry and working conditions affected on the slipper performance have been analyzed experimentally. The model of the slipper system has been established by original neural network (NN) method.

First, the effects of the slipper geometry with smooth and conical sliding surfaces on the slipper performance were experimentally analyzed. Smooth sliding surface slippers showed a better performance then the conical surface ones. According to the results, the neural predictor would be used as a predictor for possible experimental applications on modeling this type of system.

This paper discusses a new modeling scheme known as artificial NNs an experimental and a NN approach have been employed for analyzing axial piston pumps. The simulation results suggest that the neural predictor would be used as a predictor for possible experimental applications on modeling bearing system.

A two‐dimensional model for hybrid circuits is presented in this paper. Simulation results of a hybrid power module for different power dissipation of components and ambient temperature are given. The experimental contribution is based on thermal measurements of the realized hybrid power module using a matrix of flip‐chip sensors. Thermal measurements were taken at different ambient temperatures and different hybrid module power values. The temperature distributions obtained theoretically and experimentally are compared and analyzed. Finally, the contribution of the temperature distributions and measured temperatures to the reliability of the hybrid power module is given.

Demand and popularity of portable electronic devices are driving the designers to strive for higher speeds, long battery life and more reliable designs. Recently, an overwhelming interest has been seen in the problems of designing digital systems with low power at no performance penalty. Most of the very large-scale integration applications, such as digital signal processing, image processing, video processing and microprocessors, extensively use arithmetic operations. Binary addition is considered as the most crucial part of the arithmetic unit because all other arithmetic operations usually involve addition. Building low-power and high-performance adder cells are of great interest these days, and any modifications made to the full adder would affect the system as a whole. The full adder design has attracted many designer's attention in recent years, and its power reduction is one of the important apprehensions of the designers. This paper presents a 1-bit full adder by using as few as six transistors (6-Ts) per bit in its design. The paper aims to discuss these issues.

The outcome of the proposed adder architectural design is based on micro-architectural specification. This is a textual description, and adder's schematic can accurately predict the performance, power, propagation delay and area of the design. It is designed with a combination of multiplexing control input (MCIT) and Boolean identities. The proposed design features lower operating voltage, higher computing speed and lower energy consumption due to the efficient operation of 6-T adder cell. The design adopts MCIT technique effectively to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design.

The proposed adder circuit simulated results are used to verify the correctness and timing of each component. According to the design concepts, the simulated results are compared to the existing adders from the literature, and the significant improvements in the proposed adder are observed. Some of the drawbacks of the existing adder circuits from the literature are as follows: The Shannon theorem-based adder gives voltage swing restoration in sum circuit. Due to this problem, the Shannon circuit consumes high power and operates at low speed. The MUX-14T adder circuit is designed by using multiplexer concept which has a complex node in its design paradigm. The node drivability of input consumes high power to transmit the voltage level. The MCIT-7T adder circuit is designed by using MCIT technique, which consumes more power and leads to high power consumption in the circuit. The MUX-12T adder circuit is designed by MCIT technique. The carry circuit has buffering restoration unit, and its complement leads to high power dissipation and propagation delay.

The new 6-T full adder circuit overcomes the drawbacks of the adders from the literature and successfully reduces area, power dissipation and propagation delay.

This paper addresses the themes of resistance to soldering heat and heat dissipation as aspects of reliability in relation to surface mounted devices soldered on a plastic substrate by the most common industrial processes. Reliability data are presented for devices soldered by double wave, multiple wave, vapour phase and infra‐red processes and comments given on the reliability results. In terms of heat dissipation, using an internally developed test pattern and suitable test boards, a study was made of the influence of the substrate on thermal dissipation, thermal impedance, and new medium power SO and PLCC packages offering the possibility of cost‐effective power dissipation in the range of 1.5–2 W while still maintaining a standard outline.