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To determine the optimal chip/component placement for multi‐chip module (MCM) and printed circuit board (PCB) under thermal constraint.

The placement of power dissipating chips/component is carried out using genetic algorithms (GA) in order to achieve uniform thermal distribution on MCM and PCB. The thermal distribution on the MCM and PCB are predicted using 2D‐finite element method (FEM) analysis. Different number of chip/component and FEM meshing size is used to investigate the placement of chips/components.

The optimal placement of chip/component using GA is compared well to other placement techniques. The coarse meshing for FEM employed here is found adequate to carry out optimal placement of components by GA.

The analysis is valid for constant properties of MCM or PCB and steady state conditions. The chip/component size is limited to a single standard size.

The method is very useful for practical design of chip/component placement on MCM/PCB under thermal consideration.

FEM analyses of MCM and PCB can be easily implemented in the optimization procedure for obtaining the optimal chip/component placement based on thermal constraints.

Information technology (IT) systems are already ubiquitous, and their future growth is expected to drive the global economy for the next several decades. However, energy consumption by these systems is growing rapidly, and their sustained growth requires curbing the energy consumption, and the associated heat removal requirements. Currently, 20-50 percent of the incoming electrical power is used to meet the cooling demands of IT facilities. Careful co-optimization of electrical power and thermal management is essential for reducing energy consumption requirements of IT equipment. Such modeling based co-optimization is complicated by the presence of several decades of spatial and temporal scales. The purpose of this paper is to review recent approaches for handling these challenges.

In this paper, the authors illustrate the challenges and possible modeling approaches by considering three examples. The multi-scale modeling of chip level transient heating using a combination of Progressive Zoom-in, and proper orthogonal decomposition (POD) is an effective approach for chip level electrical/thermal co-design for mitigation of reliability concerns, such as Joule heating driven electromigration. In the second example, the authors will illustrate the optimal microfluidic thermal management of hot spots, and large background heat fluxes associated with future high-performance microprocessors. In the third example, data center facility level energy usage reduction through a transient measurements based POD modeling framework will be illustrated.

Through modeling based electrical/thermal co-design, dramatic savings in energy usage for cooling are possible.

The multi-scale nature of the thermal modeling of IT systems is an important challenge. This paper reviews some of the approaches employed to meet this challenge.

An automated power transistor chip sorting apparatus and position recognition algorithm have been developed at Fuji Electric. The apparatus inspects each chip on a wafer cassette, and picks out the good chips and arranges them on a chip tray cassette, at a recognition rate of 0.3 seconds per chip.

The purpose of this paper is to ensure adequate thermal management to remove and dissipate the heat produced by a light-emitting diode (LED) and to guarantee reliable and safe operation.

A three-dimensional (3-D) computational fluid dynamics (CFD) model was used to analyze the distribution of fluid velocities among microchannels at four different aspect ratios.

The results showed that at the same inlet flow rate, the larger the aspect ratio of the microchannels, the better the uniformity of the internal fluid velocity and thus better the heat dissipation performance on the surface of the high-power LED chip. In addition, the thermal performance of a high-power LED water cooling system with four different aspect ratios’ microchannel structures is further studied experimentally. Specifically, the coupling effect between the fluid velocity distribution in the microchannels and the heat dissipation performance of a high-power LED water cooling system is qualitatively analyzed and compared with the simulation results of the fluid velocity distribution. The results fully demonstrated that a larger aspect ratio of the microchannels results in better heat dissipation performance on the surface of the high-power LED chip.

Optimizing the structural parameters to facilitate a relatively uniform velocity distribution to improve the water cooling system performance may be a key factor to be considered.

The purpose of this paper is to present a fully integrated power converter. A stacked spiral inductor is applied in a voltage‐mode CMOS DC‐DC converter for the chip miniaturization and low‐power operation.

The three‐layer spiral inductor is simulated with an equivalent circuit and applied to the DC‐DC converter. The DC‐DC buck converter has been fabricated with a standard 0.35 μm CMOS process. The power converter is measured in both experiment and simulation in terms of frequency and electrical characteristics.

Experimental results show that the converter with the stacked spiral inductor operates properly with the inductance of 7.6 nH and mW power range. The measured inductance of the stacked spiral inductor is found to be almost half of the circuit designed value because of the parasitic resistances and capacitances in the spiral inductor.

This paper first introduces the application of the integrated stacked spiral inductor in DC‐DC buck converter for display driver circuit, which requires a low‐power operation. It also shows the fully integrated DC‐DC converter for chip miniaturization.

Among the main factors to be considered for the thermal optimisation of hybrid power modules are: the thermal resistance between the power chips and the bottom of the case; the thermal coupling between adjacent chips; and the ability of the module to withstand the thermal overloads induced by electrical surges. In this paper, the authors show how a finite element code can be used to optimise a hybrid power assembly in both steady‐and unsteady‐state. Comparisons made between results obtained with 3D and 2D simulations show that for hybrid power modules 2D simulations are generally unreliable. However, thermal studies cannot guarantee the reliability of hybrid power assemblies. Studies relative to hybrid power circuits must be thermomechanical.

This paper aims to study a high-temperature (up to 200 °C) data acquisition and processing circuit for logging.

With the decrease in thermal resistance by system-in package technology and exquisite power consumption distribution design, the circuit worked well at high temperatures environment from both theoretical analysis and real experiments evaluation.

In thermal simulation, considering on board chips’ power consumption as additional heat source, the highest temperature point reached by all the chips in the circuit is only 211 °C at work temperature of 200 °C. In addition, the proposed circuit was validated by long time high-temperature experiments. The circuit showed good dynamic performance during a 4-h test in a 200-°C oven, and maintained a signal-to-noise ratio of 92.54 dB, a signal-to-noise and distortion ratio of 91.81 dB, a total harmonic distortion of −99.89 dB and a spurious free dynamic range of 100.28 dB.

The proposed circuit and methodology showed great potential for application in deep-well logging systems and other high-temperature situations.

This paper presents an application of the physics‐of‐failure design philosophy to flip‐chip bonds in a microelectronic package. The physics‐of‐failure philosophy utilises knowledge of the life‐cycle load profile, package architecture and material properties to identify potential failure mechanisms and to prevent operational failures through robust design and manufacturing practices. The potential failure mechanisms and failure sites are identified in this paper for flip‐chip bonds, and an approach is presented to prevent the identified potential failure mechanisms by design. Finally, quality conformance issues are discussed to ensure a robust manufacturing process and qualification issues are addressed to evaluate the reliability of the designed flip‐chip bond.

The ever greater complexity of VLSI devices is resulting in increases in pin count, power dissipation, and chip area. Furthermore, the increase in speed because of the smaller feature sizes leads to more stringent electrical requirements on the packaging. For high reliability under adverse ambient conditions, hermetic sealing is mandatory. However, for less severe requirements, plastic encapsulation is proving a cost‐effective alternative. It is expected that improvements in plastic materials and in chip surface passivation will further enhance the reliability of plastic‐packaged VLSI devices. Packaging materials and processes, as well as packaged shapes, will have to be modified to cope with the demands of future VLSI devices.

As requirements for system performance and density increase, more attention is being given to chip‐on‐board (COB) packaging techniques. COB is ‘surface mount packaging taken to the extreme’ as it involves the direct mounting of bare semiconductor die to printed circuit board substrates. In this paper, the ‘thermal resistance’ of a single COB package is proposed. An analytical model for this resistance is developed for a multilayer board configuration using a combination of Fourier transform and adjoint‐solution techniques. Parameters in the model include the chip and board geometric parameters, individual layer unit conductances, and top and bottom surface film coefficients. A series of curves are developed from the model. These curves may be used in the initial design process to determine, for example, required film coefficients and the efficacy of adding thermal planes to the board. The model is also used to test the adequacy of the ‘effective series conductivity’ of a multilayer board.