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The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE).

The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (g_m3) to be canceled with the main PA’s fixed negative g_m3. The g_m3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity.

For driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc.

In this study, a novel cascaded g_m3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications.

A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks.

By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm² and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz.

The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.

The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA).

The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of C_gs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability.

With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation.

The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design.

The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

The purpose of this study is to show that due to the emergence of the Internet of Things (IoT) industry in recent years, the demand for the higher integration of wireless communication systems with a higher data rate of transmission capacity and lower power consumption has increased tremendously. The radio frequency power amplifier (PA) design is getting more challenging and crucial. A PA for a 2.45 GHz IoT application using 0.18 µm complementary metal oxide semiconductor (CMOS) technology is presented in this paper.

The design consists of two stages, the driver and output stage, where both use a single-stage common source transistor configuration. In view of performance, the PA can deliver more than 20 dB gain from 2.4 GHz to 2.5 GHz.

The maximum output power achieved by PA is 13.28 dBm. As the PA design is targeted for Bluetooth low energy (BLE) transmitter use, a minimum of 10 dBm output power should be achieved by PA to transmit the signal in BLE standard. The PA exhibits a constant output third-order interception point of 18 dBm before PA becomes saturated after 10 dBm output power. The PA shows a peak power added efficiency of 17.82% at the 13.24 dBm output power.

The PA design exhibits good linearity up to 10 dBm out the PA design exhibits good linearity up to 10 dBm output power without sacrificing efficiency. At the operating frequency of 2.45 GHz, the PA exhibits a stability k-factor, the value of more than 1; thus, the PA design is considered unconditional stable. Besides, the PA shows the s-parameters performance of –7.91 dB for S11, –11.07 dB for S22 and 21.5 dB for S21.

This paper aims to implement a new high output power fully integrated 23.1 to 27.2 GHz gallium arsenide heterojunction bipolar transistor power amplifier (PA) to meet the stringent linearity requirements of LTE systems.

The direct input power dividing technique is used on the chip. Broadband input and output matching techniques are used for broadband Doherty operation.

The PA achieves a small-signal gain of 22.8 dB at 25.1 GHz and a saturated output power of 24.3 dBm at 25.1 GHz with a maximum power added efficiency of 31.7%. The PA occupies 1.56 mm² (including pads) and consumes a maximum current of 79.91 mA from a 9 V supply.

In this paper, the author proposed a novel direct input dividing technique with broadband matching circuits using a low Q output matching technique, and demonstrated a fully-integrated Doherty PA across frequencies of 23.1∼27.2 GHz for long term evolution-license auxiliary access (LTE-LAA) handset applications.

The purpose of this paper is to design and realize a high gain power amplifier (PA) with low output back-off power using the InGaP/GaAs HBT process for WCDMA applications from 1.85 to 1.91 GHz.

A three stages cascaded PA is designed which observes a high power gain. A 100 mA of quiescent current helps the PA to operate efficiently. The final stage device dimension has been selected diligently in order to deliver a high output power. The inter-stage match between the driver and main stage has been designed to provide maximum power transfer. The output matching network is constructed to deliver a high linear output power which meets the WCDMA adjacent channel leakage ratio (ACLR) requirement of −33 dBc close to the 1 dB gain compression point.

With the cascaded topology, a maximum 31.3 dB of gain is achieved at 1.9 GHz. S11 of less than −18 dB is achieved across the operating frequency band. The maximum output power is indicated to be 32.7 dBm. An ACLR of −33 dBc is achieved at maximum linear output power of 31 dBm.

The designed PA is an excellent candidate to be employed in the WCDMA transmitter chain without the aid of additional driver amplifier and linearization circuits.

In this work, a fully integrated GaAs HBT PA has been implemented which is capable to operate linearly close to its 1 dB gain compression point.

The purpose of this paper is to investigate the temperature reliability for a parallel high-efficiency class-E power amplifier (PA).

To explore the relationship between temperature and direct current (DC) characteristics, output power, S parameters and efficiency of the PA quantitatively, a series of reliability experiments have been designed and conducted to study the temperature reliability for this PA.

From the results, the prominent performance degradation even failure is found during the testing. Furthermore, the thermal shock test can cause permanent failure, which is a great threat for PA.

Therefore, to ensure the good performance, the influence of temperature on PA reliability should be carefully considered during the stage of PA design.

All these can provide important guidance for the reliability design of PA.

All these can give some important guidance for PA application.

In addition, PA is usually designed according to the electrical properties at the room temperature. From the results above, it can be concluded that it may be unable to satisfy the performance requirement at high temperature. In turn, if it is designed according to the electrical properties at low temperature, the transistor often works in the super-saturated state, the reliability of PA will become the new problem. Therefore, to ensure the good performance, the influence of temperature on PA reliability should be carefully considered during the design.

The design and implementation of a broadband quasi-monolithic microwave integrated circuit (q-MMIC) power amplifier (PA) is presented for 0.2 to 2.2 GHz applications.

To obtain an efficient, high-gain and high-power performance with in a compact and low-cost size, the prototype is based on Gallium nitride (GaN) on SiC 0.25-µm transistors, whereas the passive matching networks are realized on an AlN substrate as thin film circuit.

Measured results of the q-MMIC PA across the 0.2 to 2.2 GHz band show at least 32 ± 3 dB small-signal gains, an output power of 7 to 12 W and an average power add efficiency greater than 54%. The q-MMIC occupies an area of 12.8 × 14.5 mm².

To the best of the authors’ knowledge, this work reports the first full integrated PA which covers the frequency range of 0.2 to 2.2 GHz and achieves the combination of highest gain, about 10 W output power, together with the smallest component size among all published GaN PAs to date.

The paper aims to focus on the memory-polynomial model (MPM) as special case of Volterra series, implemented in hardware. The behavior of the MPM is fully proved through a comparison with AM-AM and AM-PM measured data. The results show that this simulation technique is able to prove the effectiveness of the MPM implementation as behavioural model for high power radiofrequency amplifiers. The system is able to compensate perturbations caused by modern communication systems.

The implementation uses Matlab-Simulink, and its digital signal processing (DSP) builder. The first stage allows developing the model in Matlab using the DSP builder blockset through the signal compiler block. Then, the design is downloaded to the DSP board.

The paper demonstrates a proper behavior of the MPM as a truncation of the Volterra series, with respect to different inputs. This is a key point, because the series truncations allow first to implement this model in real time and second to obtain a correct precision, for instance when modeling amplification of digital signals in high frequency.

The global system approach permits to easily develop, simulate, and validate a wireless system. The efficiency of a complete connected solution based on Agilent Technologies tools, combining simulations and measurements under true operating conditions, seems to be clearly demonstrated.

The purpose of this paper is to develop a model of the inductive link for implantable systems. The model is suitable for a cochlear implant in which a lateral misalignment and distance coil can be up to 16 mm.

The description of the generation of implantable systems' high‐power, such as a cochlear implant, are powered by transcutaneous inductive power links formed by two coils: the first is a printed spiral coil used in the receiver device and the second is a solenoid coil used in the emitter device. Optimizing the power efficiency of the wireless link is imperative to minimize the size of the external energy source, heating dissipation in the tissue, and interference with other devices. The authors have outlined the theoretical foundation of optimal power transmission efficiency in an inductive link, and combined it with semi‐empirical models to predict parasitic components. The power amplifier itself is a class‐E amplifier optimized in both output voltage and efficiency, and bears an excellent tolerance to misalignments.

Two Spice‐based electrical models of the coils are achieved. The technique employed during the work is based on polynomial interpolation of the mutual inductance in which coil misalignments are considered as variables. On the other hand, a voltage regulator is studied and simulated by Cadence Analog Artist in the AMS 0.35 μm CMOS technology.

This paper provides a novel and useful method for transmitting power for an implantable system via an inductive link. The procedure of the authors' design is achieved at 10 MHz and the power transmission efficiency is 35 percent, whatever the longitudinal misalignment (up to 16 mm) between both coils.