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This paper aims to present an 8 kW LLC resonant converter designed for plasma power supply with higher efficiency and lighter structure. It presents how to solve the problems of large volume and weight, low performance and low efficiency of traditional plasma power supply.

At present, conventional silicon (Si) power devices’ switching performance is close to the theoretical limit determined by its material properties; the next-generation silicon carbide (SiC) power devices with outstanding advantages can be used to optimal design. This 8 kW LLC resonant converter prototype with silicon carbide (SiC) power devices with a modulated switching frequency ranges from 100  to 400 kHz.

The experimental results show that the topology, switching loss, rectifier loss, transformer loss and drive circuit of the full-bridge LLC silicon carbide (SiC) plasma power supply can be optimized.

Due to the selected research object (plasma power supply), this study may have limited universality. The authors encourage the study of high frequency resonant converters for other applications such as argon arc welding.

This study provides a practical application for users to improve the quality of plasma welding.

The experimental results show that the full-bridge LLC silicon carbide (SiC) plasma power supply is preferred in operation under conditions of high frequency and high voltage. And its efficiency can reach 98%, making it lighter, more compact and more efficient than previous designs.

Poisson’s equation and the electron continuity equation, together with heat flow equation are solved self‐consistently to obtain the lattice temperature profile under non‐isothermal conditions in a power VDMOS transistor. The effect of the variable lattice temperature on the forward characteristics of VDMOSTs is presented, and discussed. The results show that self‐heating in power VDMOSTs has a significant effect. The thermal coupling effects on the forward I—V characteristics are compared and discussed between the power VDMOST and the conventional MOSFET.

The purpose of this paper is to design and construct a low‐cost current‐voltage tester, bearing in mind the short falls of the existing testers and the ever‐increasing price of the testers currently on the market. The I‐V tracer presented in this paper uses a variable external power supply unit (PSU) as the load, in order to obtain the entire operating range of a PV module from open circuit through maximum power to short circuit condition.

The I‐V tracer presented in this paper was divided into three main sections, mainly the data acquisition system (DAS), which comprises an A/D computer card, temperature card, electromechanical relays, current and voltage transducers, aluminum housed resistors and power MOSFETS, the variable load (programmable variable PSU) and finally the signal processing unit. These components were integrated and finally interfaced to a PC.

The results obtained using this system compared with the capacitive tester show a low percentage difference of <1 from the comparative I‐V curves measured. The results measured by the PSU tester are also of high accuracy. The findings also demonstrated the fact that most of the components found in most university laboratories can be used to build the PSU tester and still obtain highly accurate results.

Since some components are semiconductors, which have a limited lifetime, they need to be changed if they fail. Mostly the MOSFETS should be replaced when no switching signal is sent.

This low‐cost PSU tester is suitable for researchers in disadvantaged institutions whose research capabilities are limited due to the high cost of this equipment.

The PSU tester uses a variable power supply as the load to measure PV module I‐V curves. The system is capable of measuring up to eight modules at the same time, making it possible to analyze PV modules within the same time frame.

This paper aims to present a new wireless power transfer technique using capacitive coupling. The capacitive power transfer (CPT) system has been introduced as an attractive alternative to the traditional inductive coupling method. The CPT offers benefits such as simple topology, fewer components, better electromagnetic interference (EMI) performance and robustness to surrounding metallic elements.

A class-E inverter together with and without inductor capacitor (LC) matching circuit has been utilised in this work because of its ability to perform the DC-to-AC inversion efficiently with significant reduction in switching losses. The validity of the proposed concept has been verified by conducting a laboratory experiment of the CPT system.

The performances for both systems are analysed and evaluated. A 9.7 W output power is generated through a combined interface [printed circuit board (PCB) plate] capacitance of 2.82 nF at an operating frequency of 1 MHz, with 97 per cent efficiency for 0.25 mm coupling gap distance.

An efficient CPT system with class-E LC matching topology is proposed in this paper. With this topology, the zero-voltage switching can be achieved even if the load is different by properly designing the LC matching transformation circuit.

Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention.

The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state.

A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption.

Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

The purpose of this paper is to a provide short introductory overview of metal in board (MiB) circuit technologies for use in thermal management applications.

The paper details the types of metal in printed circuit boards (PCBs) that are possible and the mix of key features each exhibits. These combinations offer a mix of capabilities in thermal management, current conduction, interconnect density, material usage and cost that can be chosen to suit a specific application. Examples of these board types and their uses are considered.

Metal core and insulated metal substrate (IMS) PCBs are categories of PCB technologies which provide enhanced thermal management and current carrying capability. MiB technologies are based on conventional printed circuit materials and processes. This gives MiB a range of thermal and current handling characteristics which are particularly suited to a number of key existing and emerging applications.

Further research and development in materials, processes and designs will help broaden the applicability of these types of boards, enabling them to encompass even more thermal management applications.

The paper shows that with 15 different types of metal core and metal backed PCB technologies available to handle thermal dissipation in power electronics, there is one to suit almost every application. This current and emerging portfolio of MiB types offers solutions which can handle thermal loads associated with power densities from about 0.25 W/cm² to 10‐15 W/cm² and currents from 20 A up to approximately 1000 A.

The aim of this paper is to present non-destructive and destructive methods of failure analysis of epoxy moulded IC packages on the example of power MOSFETs in SOT-227 package.

A power MOSFET in SOT-227 package was examined twice using X-ray inspection, at first as the whole component to check if it is damaged and then after removing the upper part of package by mechanical grinding. The purpose of the second X-ray inspection was to prepare images for estimation of the total number and approximate location of voids in soft solder layers. Finally, power MOSFETs were subjected to decapsulation process using a concentrated sulphuric acid to verify existence of damage areas noticed during X-ray analysis and to observe other possible failures such as cracks in aluminium metallization or wires deformation.

X-ray analysis was revealed to be adequate technique to detect damage (e.g. meltings) in power MOSFETs in SOT-227 package, but only when tested components were analysed in the side view. This type of analysis combined with a graphic software is also suitable for voids estimation in soft solder layers. Moreover, it was found that a single acid (concentrated sulphuric acid) at elevated temperature can be successfully used for decapsulation of power MOSFETs in SOT-227 package without damage of aluminium metallization and aluminium wires. Such decapsulation process enables analysis of defects in wire, die and package materials.

Further investigations are required to examine if the presented methods of failures analysis can be used for other types of components (e.g. high power resistors) in similar packages.

The described methods of failure analysis can find application in electronic industry to select components which are free of damage and in effect which allow to produce high reliable devices. Apart from it, the presented method is applicable to evaluate reasons of improper work of tested electronic devices and to identify faked components.

This paper contains valuable information for research and technical staff involved in the assessment of electronic devices who needs practical methods of failure analysis of epoxy moulded IC packages.

This paper aims to characterize the relationship between the interelectrode capacitance (C) of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the applied bias voltage (V) by a fractional-order equivalent model.

A Riemann–Liouville-type fractional-order equivalent model is proposed for the C–V characteristic of MOSFETs, which is based on the mathematical relationship between fractional calculus and the semiconductor physical model for the interelectrode capacitance of metal oxide semiconductor structure. The C–V characteristic data of an N-channel MOSFET are obtained by Silvaco TCAD simulation. A differential evolution-based offline scheme is exploited for the parameter identification of the proposed model.

According to the results of theoretical analysis, mathematical derivation, simulation and comparison, this paper illustrates that, along with the variation of bias voltage applied, the interelectrode capacitance (C) of MOSFETs performs a fractional-order characteristic.

This work uncovers the fractional-order characteristic of MOSFETs’ interelectrode capacitance. By the proposed model, the influence of doping concentration on the gate leakage parasitic capacitance of MOSFETs can be revealed. In the pre-defined doping concentration range, the relative error of the proposed model is less than 5% for the description of C–V characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs). Compared to some existing models, the proposed model has advantages in both model accuracy and model complexity, and the variation of model parameters can directly reflect the relationship between the characteristics of MOSFETs and the doping concentration of materials. Accordingly, the proposed model can be used for the microcosmic mechanism analysis of MOSFETs. The results of the analysis produce evidence for the widespread existence of fractional-order characteristics in the physical world.