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Outgassing of PTH PCBs at different stages of PCB production was studied with a modified IEC outgassing test, Draft June 1985, now included in IEC 326–2 Amendment No. 2…
Outgassing of PTH PCBs at different stages of PCB production was studied with a modified IEC outgassing test, Draft June 1985, now included in IEC 326–2 Amendment No. 2, January 1988. Outgassing rate from single PTHs was quantitatively measured with a U‐tube manometer as a pressure of expanded steam escaped. Some technological parameters were taken into account and different comparisons were made: PCB production stage (drilling, copper and solder plating, reflowing) vs. outgassing rate, laminate thickness vs. outgassing rate. The contributions to outgassing of PTHs through PCB production, especially from copper and tin‐lead plating, are seen. On PCBs, drilled with different drills and soldered unpopulated on wave and drag soldering machines, outgassing faults were assessed. By multiple regression the relation between outgassing faults, hole wall roughness and plated copper thickness was calculated.
The paper gives design guidelines for polymer thick‐film technology (PTF). After an introduction reviewing the main PTF properties, materials and processes, detailed PTF…
The paper gives design guidelines for polymer thick‐film technology (PTF). After an introduction reviewing the main PTF properties, materials and processes, detailed PTF design rules are presented. They are conservative, to achieve high production yield. The design rules are based on the considerable experience in the companies of the authors and of the persons mentioned in the acknowledgements, as well as on information from the open literature and from materials suppliers. The design guidelines are intended primarily for designers, but they are also important for production personnel, to facilitate a close coupling between design and production, and thus provide optimum use of PTF and obtain high production yield.
This paper describes the use of the EE‐1 process for making high‐reliability multilayer boards. The EE‐1 process eliminates the need for flash electroless copper for plated…
This paper describes the use of the EE‐1 process for making high‐reliability multilayer boards. The EE‐1 process eliminates the need for flash electroless copper for plated‐through holes. With this process, copper is directly electrodeposited onto an activated through‐hole. In addition to eliminating electroless deposition, the EE‐1 process claims to simplify process control, provide excellent copper‐to‐copper adhesion, and total backlight PTH coverage. Production experience with the process is extensive as it has been used at Photocircuits, Atlanta, since January 1986 in the fabrication of double‐sided boards. Test data of joint reliability and physical properties of copper in PTHs of multilayer boards obtained through this unique approach are presented. A special test, which directly measures the bond strength between through‐hole deposited copper and inner foil of multilayers, is also discussed.
Thermal cycling tests and failure modelling were conducted on FR‐4 and cyanate ester printed circuit board (PCB) substrate materials to evaluate reliability limits tor…
Thermal cycling tests and failure modelling were conducted on FR‐4 and cyanate ester printed circuit board (PCB) substrate materials to evaluate reliability limits tor solder and repair processes, particularly for high pin count, through‐ hole devices. The boards used were double‐sided, 0.125 in. thick with 0.029 in. diameter plated‐through holes (PTHs). Thermal cycling was accomplished using hot oil immersion at 240°C and 260°C followed by forced room‐temperature air. The average number of thermal cycles‐to‐failure was 10 for FR‐4, 20 for cyanate ester epoxy blend, and 50 for cyanate ester. Weibull statistics were used to predict failure rates for various pin count devices. Failure analysis was used to identify the mechanism of failure, and modelling was used to predict cycles‐to‐failure based on typical material properties. The primary failure mechanism was corner cracking in FR‐4 and a combination of corner cracking and barrel cracking in the cyanate ester materials. The modelling used a modified pad tilt geometry combined with Coffin‐Manson low cycle fatigue theory, which resulted in predictions of the same order as those for the cycling tests. Key material properties and process parameters were identified that controlled the failure response of the plated‐through hole and board substrate combinations.
The purpose of this paper is to present a summary of development work made in technical centres and on the subsequent customer qualification of copper filled through holes…
The purpose of this paper is to present a summary of development work made in technical centres and on the subsequent customer qualification of copper filled through holes and blind microvias.
Various copper deposition parameters were investigated in a small‐scale production line which was then extended to full‐scale production qualification in a horizontal conveyorised system. Samples of substrates with copper filled through holes were qualified at end‐user facilities.
The copper plating process may be used to replace an existing production process for printed circuit boards. The proposed system can give a more reliable result in terms of filling and technical capability for the produced substrate. Overall production cost savings are possible.
The technology is based on a copper plating electrolyte using a redox pair for copper replenishment. The results achieved depend on use of this system and on production equipment which can control the redox system and copper concentration within a tight range.
The paper shows how the use of a horizontal production system with redox copper replenishment can achieve filling of though holes and blind microvias with reduced surface plated copper thickness. Reduction in the use of copper saves both resources and also reduces production costs. The process is proposed as an alternative to existing paste plugging processes, which are both cost and labour intensive.
The failure of copper‐plated holes in dielectric laminates during thermal cycling is a serious problem for the electronics industry. The large difference in out‐of‐plane…
The failure of copper‐plated holes in dielectric laminates during thermal cycling is a serious problem for the electronics industry. The large difference in out‐of‐plane thermal expansion between the dielectric laminate and the copper plating can cause the copper plating to deform and fail as the board is thermally cycled. The purpose of this study was to demonstrate the feasibility of using electro‐optic holographic interferometry (EOHI) to measure deformation around plated holes and to evaluate methods for estimating the stress in the barrel plating. It was demonstrated that EOHI was more than adequate to resolve the out‐of‐plane thermally induced displacement field around an array of plated‐through holes. The displacement sensitivity was better than ±10 nm with high spatial resolution (92 ?m horizontally and 75 ?m vertically).The expansion was reasonably linear from 30°C to 120°C. The deformation around the individual holes was not axisymmetric. It is suggested that the method for estimating barrel stresses may be too sensitive to thickness and architecture variations in the pad for reliable stress estimates. An alternative scheme for estimation of barrel stresses based on thermal strain energy evaluation is described.
Solder masks are used universally on high density printed circuit boards to reduce the occurrence of solder bridges between adjacent tracks and pads. The use of solder mask can, however, have a deleterious effect on the solderability, i.e., the solder pull‐through and top‐land wetting, of plated‐through‐hole boards. This work considers, quantitatively, the specific effect on PTH board solderability of solder mask, considering in turn the three classes of photoimageable dry film, photoimageable ink and screen printed ink. Two modes of solderability degradation have been identified: a geometrical effect that depends on the thickness of the mask and its encroachment around the solderable pads, and a contamination effect arising from the development and washing of the photoimageable masks from surfaces to be soldered subsequently.
Reviews stencil design requirements for printing solder paste around and in through‐hole pads/openings. There is much interest in this procedure since full implementation…
Reviews stencil design requirements for printing solder paste around and in through‐hole pads/openings. There is much interest in this procedure since full implementation allows the placement of both through‐hole components as well as surface mount devices and the subsequent reflow of both simultaneously. This in turn eliminates the need to wave solder or hand solder through‐hole components. The effect of component material type, pin type, lead length, and standoff height of the through hole components is reviewed. Board design issues including plated through‐hole size, pad size, board thickness, and solder mask type are also reviewed. Three stencil designs are considered: single thickness stencils with oversized stencil apertures for overprinting solder paste in the through‐hole pad areas; step stencils with oversized stencil apertures for overprinting solder paste in the through‐hole pad areas; thick stencils (0.384‐0.635 mm thick) for printing solder paste in the through‐hole pad areas. The latter thick stencil is the second stencil in the two‐print stencil process. Several examples are reviewed with the recommended stencil designs.
The purpose of this paper is to investigate if copper nanoparticles could be utilized for two types of through hole plating in printed circuit boards, namely: as a…
The purpose of this paper is to investigate if copper nanoparticles could be utilized for two types of through hole plating in printed circuit boards, namely: as a catalytic material to initiate the electroless copper deposition process; and as a “conductive” layer which is coherent and conductive enough to allow “direct” electroplating of the through hole. The employment of nanoparticles means that an effective method of dispersion is required and this paper studies the use of mechanical agitation and ultrasound for this purpose.
The paper utilized drilled, copper clad FR4 laminate. The through holes were functionalized using a commercially available “conditioner” before being immersed in a solution of copper nanoparticles which were dispersed using either a magnetic stirrer or ultrasound (40 kHz). When the copper nanoparticles were utilized as a catalytic material for electroless copper plating, the efficacy of the technique was assessed using a standard “backlight” test which allowed the plating coverage of the through holes to be determined. As a control, a standard palladium catalysed electroless copper process was employed. The morphology of the electroless copper deposits was also analysed using scanning electron microscopy. In the “direct plate” approach, after immersion in the copper nanoparticle dispersion, the through holes were electroplated at 3 Adm−2 for 15 min, sectioned and examined using an optical microscope. The distance that the copper electroplate had penetrated down the through hole was then determined.
The paper has shown that copper nanoparticles can be used as a catalytic material for electroless copper plating. The coverage of the electroless copper in the through hole improves as the copper nanoparticle concentration increases and, at the highest copper nanoparticle concentrations employed, good, but not complete, electroless copper coverage is obtained. Dispersion of the copper nanoparticles using ultrasound is critical to the process. Ultrasonically dispersed copper nanoparticles achieve some limited success as a conductive layer for “direct” electroplating with some penetration of the electroplated deposit into the through hole. However, if mechanical agitation is employed to mix the nanoparticles, no through hole plating obtaines.
The paper has demonstrated the “proof of concept” that copper nanoparticles can be utilized to catalyse the electroless copper process, as well as their potential to replace costly palladium‐based activators. The paper also illustrates the potential for copper nanoparticles to be used as a “direct plate process” and the necessity for using ultrasound for their dispersion in either process.
Various methods are described of making separable electrical connections to MID structures. The first part discusses the use of a copper plated, glass filled plastic substrate as a contact surface. It is shown that the morphology is different from that of conventional contacts due to the presence of dendritic growths, further that mechanical properties like stiffness and strength are lower than for solid copper. The second part discusses the application of two conventional techniques ‐ elastromeric connectors and compliant pins. Elastomeric connectors are designed to form a high density, separable interface using gold plated conductors. Compliant pins pressed into plated‐through holes form very reliable, high normal force connections without the need for noble metal plating. Two compliant pin designs have been tested with plated holes in two versions, moulded and drilled. All combinations show excellent electrical stability; however, differences were found in mechanical behaviour between the various pin and hole combinations.