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Article
Publication date: 30 October 2018

Satyabrata Dash, Sukanta Dey, Deepak Joshi and Gaurav Trivedi

The purpose of this paper is to demonstrate the application of river formation dynamics to size the widths of power distribution network for very large-scale integration…

Abstract

Purpose

The purpose of this paper is to demonstrate the application of river formation dynamics to size the widths of power distribution network for very large-scale integration designs so that the wire area required by power rails is minimized. The area minimization problem is transformed into a single objective optimization problem subject to various design constraints, such as IR drop and electromigration constraints.

Design/methodology/approach

The minimization process is carried out using river formation dynamics heuristic. The random probabilistic search strategy of river formation dynamics heuristic is used to advance through stringent design requirements to minimize the wire area of an over-designed power distribution network.

Findings

A number of experiments are performed on several power distribution benchmarks to demonstrate the effectiveness of river formation dynamics heuristic. It is observed that the river formation dynamics heuristic outperforms other standard optimization techniques in most cases, and a power distribution network having 16 million nodes is successfully designed for optimal wire area using river formation dynamics.

Originality/value

Although many research works are presented in the literature to minimize wire area of power distribution network, these research works convey little idea on optimizing very large-scale power distribution networks (i.e. networks having more than four million nodes) using an automated environment. The originality in this research is the illustration of an automated environment equipped with an efficient optimization technique based on random probabilistic movement of water drops in solving very large-scale power distribution networks without sacrificing accuracy and additional computational cost. Based on the computation of river formation dynamics, the knowledge of minimum area bounded by optimum IR drop value can be of significant advantage in reduction of routable space and in system performance improvement.

Details

Journal of Systems and Information Technology, vol. 20 no. 4
Type: Research Article
ISSN: 1328-7265

Keywords

Article
Publication date: 15 May 2009

Ki‐Jae Song, Jongmin Kim, Jongwoon Yoo, Wansoo Nah, Jaeil Lee and Hyunseop Sim

The purpose of this paper is to present the power noise characteristics of a multilayer printed circuit board (PCB) in which discrete capacitors have been embedded.

Abstract

Purpose

The purpose of this paper is to present the power noise characteristics of a multilayer printed circuit board (PCB) in which discrete capacitors have been embedded.

Design/methodology/approach

Embedded technology has been implemented on a multilayer PCB to enhance the performance and functionality and to decrease the power noise. Decoupling capacitors were directly positioned on the inner power planes of a board, which resulted in low‐loop inductance through the minimized length of the interconnection from the chips to the PCB's power delivery network.

Findings

A low‐noise PCB was successfully designed and fabricated using an embedding process for the discrete decoupling capacitors. It was demonstrated that such an approach offers lower interconnection inductance and quiet noise performance, including highly efficient propagation noise suppression at wideband frequencies.

Research limitations/implications

Most conventional simulation techniques offer expectations for the signal characteristics on the time domain to minimize bit error rates in application systems. Further development work will focus on the integrated simulation models including the equivalent circuits for the transmission line and power noise effects to improve the accuracy of the signal performance.

Originality/value

This paper presents a new approach for improving generating and propagating noise performance through the use of an embedded decoupling capacitor design methodology.

Details

Circuit World, vol. 35 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 1 April 1988

Andrew Buxton

JANET(the Joint Academic Network) is a wide‐area network linking together computers and users in British universities, polytechnics, establishments of the research…

Abstract

JANET(the Joint Academic Network) is a wide‐area network linking together computers and users in British universities, polytechnics, establishments of the research councils, and the British Library. It provides for interactive working, file transfer, electronic mail and job transfer. Online access is possible to many catalogues of university and polytechnic libraries, the British Library's BLAISE‐LINE and ARTel services, and various bibliographic and numeric databases held on university computers. Users registered for electronic mail can use Janet to send this kind of mail to other sites in Britain, or overseas through the EARN, BITNET, and NORTHNET combined network. There are two‐way gateways between Janet and British Telecom network PDN, allowing access to commercial online hosts in Great Britain or overseas. These gateways can provide a faster and cheaper alternative to dial‐up use of PDN.

Details

The Electronic Library, vol. 6 no. 4
Type: Research Article
ISSN: 0264-0473

Article
Publication date: 23 August 2011

Happy Holden and Charles Pfeil

High‐density interconnect (HDI) continues to be the fastest growing segment of the printed circuit board (PCB) market. The purpose of this paper is to discuss the…

1516

Abstract

Purpose

High‐density interconnect (HDI) continues to be the fastest growing segment of the printed circuit board (PCB) market. The purpose of this paper is to discuss the differences in designing HDI compared to conventional PCB multilayers. This is important for the challenging aspects of very high‐speed electronics that require care to control signal integrity and power integrity.

Design/methodology/approach

Eight new design principles were studied and illustrated with emphasis on how these differ from conventional PCB design.

Findings

HDI implementation can be improved 2X to 4X by employing these new design principles. Densities from 6‐12 in. per sq. inch to 18‐48 in. per sq. inch have been reported. Design time reductions of 50 percent and cost reductions of 30 percent were also seen.

Research limitations/implications

This work was focused on the basic design principles and does not address electronics design automation tools or specific design steps. PCB design is a complex activity and readers are encouraged to obtain and use the references cited.

Originality/value

The paper describes various design and layout procedures that the authors have learned over the last 29 years involved in printed circuit design and fabrication. These principles can be combined with other innovations to enable a much more beneficial use of HDI technologies.

Abstract

Details

Cognitive Economics: New Trends
Type: Book
ISBN: 978-1-84950-862-9

Article
Publication date: 9 February 2010

Mohammed A. Alam, Michael H. Azarian, Michael Osterman and Michael Pecht

The purpose of this paper is to present an analytical approach to find the reduction in the required number of surface mount capacitors by the use of embedded capacitors…

Abstract

Purpose

The purpose of this paper is to present an analytical approach to find the reduction in the required number of surface mount capacitors by the use of embedded capacitors in decoupling applications.

Design/methodology/approach

The analytical model used to perform decoupling is cavity model from theory of microstrip antenna and N‐port impedance matrix. The methodology involves addition of decoupling capacitors between the power and the ground plane such that the impedance between ports on the power‐ground plane becomes lower than the target impedance at that frequency. A case study is presented in which a 0.3 m×0.3 m power‐ground plane is decoupled by using various combinations of surface mount capacitors and embedded capacitors in the frequency range of 0.001‐1 GHz and at a target impedance of 0.1, 0.01, and 0.001 Ω. The total number of surface mount capacitors are compared in each case.

Findings

Use of embedded planar capacitors with a thin dielectric (about 8 mm) dampened board resonances at high frequency, as compared to a thick dielectric. Embedded capacitors are found to reduce the number of surface mount capacitors when the target impedance is low and the operating frequency is high.

Research limitations/implications

The methodology discusses in this paper is applicable to a simplified power‐ground plane (which has no cut‐outs and is rectangular in shape) as compared to actual digital circuits.

Originality/value

This methodology can be used as a quick preliminary tool to evaluate the decrease in the number of surface mount capacitors (by the use of embedded capacitors) as compared to complex and time consuming electromagnetic solvers.

Details

Circuit World, vol. 36 no. 1
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 1 June 1991

Judith Carter

Discusses the user facilities offered by the PRISM service.Considers the benefits in moving among bibliographic records of thecommands which differentiate PRISM from…

Abstract

Discusses the user facilities offered by the PRISM service. Considers the benefits in moving among bibliographic records of the commands which differentiate PRISM from previous systems. Demonstrates the use of PRISM through a step‐by‐step guide to a specific author search, recommending practice to polish user skills with the new commands.

Details

OCLC Micro, vol. 7 no. 6
Type: Research Article
ISSN: 8756-5196

Keywords

Article
Publication date: 1 May 1970

YOU cannot see the bearings for dust in the new rig for testing triple seals on ball bearings at the Northampton Test Centre of Ransome Hoffmann Pollard Ltd. (RHP). The…

Abstract

YOU cannot see the bearings for dust in the new rig for testing triple seals on ball bearings at the Northampton Test Centre of Ransome Hoffmann Pollard Ltd. (RHP). The rig has been designed for the PDN and PDNF series which are mainly used in agricultural machinery.

Details

Industrial Lubrication and Tribology, vol. 22 no. 5
Type: Research Article
ISSN: 0036-8792

Article
Publication date: 1 January 1992

Claire B. Dunkle

Outlines a training programme developed for infrequent users ofOCLC who are apt to be discouraged by OCLC′s new PRISM interface.Addresses means of developing training…

Abstract

Outlines a training programme developed for infrequent users of OCLC who are apt to be discouraged by OCLC′s new PRISM interface. Addresses means of developing training participants′ confidence and ways of making OCLC activities more enjoyable.

Details

OCLC Micro, vol. 8 no. 1
Type: Research Article
ISSN: 8756-5196

Keywords

Abstract

Details

Mental Health Review Journal, vol. 8 no. 1
Type: Research Article
ISSN: 1361-9322

1 – 10 of 68