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This work focused on a basic building block of an allocation unit that carries out the critical job of deciding between the conflicting requests, i.e. an arbiter unit. The purpose of this work is to implement an improved hybrid arbiter while harnessing the basic advantages of a matrix arbiter.

The basic approach of the design methodology involves the extraction of traffic information from buffer signals of each port. As the traffic arrives in the buffer of respective ports, information from these buffers acts as a source of differentiation between the ports receiving low traffic rates and ports receiving high traffic rates. A logic circuit is devised that enables an arbiter to dynamically assign priorities to different ports based on the information from buffers. For implementation and verification of the proposed design, a two-stage approach was used. Stage I comprises comparing the proposed arbiter with other arbiters in the literature using Vivado integrated design environment platform. Stage II demonstrates the implementation of the proposed design in Cadence design environment for application-specific integrated chip level implementation. By using such a strategy, this study aims to have a special focus on the feasibility of the design for very large-scale integration implementation.

According to the simulation results, the proposed hybrid arbiter maintains the advantage of a basic matrix arbiter and also possesses the additional feature of fault-tolerant traffic awareness. These features for a hybrid arbiter are achieved with a 19% increase in throughput, a 1.5% decrease in delay and a 19% area increase in comparison to a conventional matrix arbiter.

This paper proposes a traffic-aware mechanism that increases the throughput of an arbiter unit with some area trade-off. The key feature of this hybrid arbiter is that it can assign priorities to the requesting ports based upon the real-time traffic requirements of each port. As a result of this, the arbiter is dynamically able to make arbitration decisions. Now because buffer information is valuable in winning the priority, the presence of a fault-tolerant policy ensures that none of the priority is assigned falsely to a requesting port. By this, wastage of arbitration cycles is avoided and an increase in throughput is also achieved.

I was an invited speaker to the ISHM‐Benelux meeting. As I arrived early, I also sat in on the committee meeting as an observer. Jos B. Peeters was the outgoing president and the incoming committee was widened to about 15 members compared with the previous 6. Following the unanimous election of all those nominated, the committee reconvened and elected Mr Kwikkers as the new president of ISHM‐Benelux. He is a professor at the Technische Hogeschole in Delft.

ISHM‐Benelux held its 1987 Autumn Conference on 29 October, at the Antwerp Crest Hotel. This one‐day meeting focused on applications of hybrid circuit technology in various fields of electronic and related industries.

This article aims to provide details of recent research into image sensing technologies.

Following an introduction, this article discusses image sensing research involving a range of new materials, novel designs and signal processing schemes. It concludes with a brief discussion of a potentially game-changing technology, the quanta image sensor.

This shows that image sensing is the topic of a major academic and corporate research effort. It involves a diversity of technologies and seeks to yield devices with enhanced or unique characteristics.

This article provides a timely review of recently reported research into image sensing.

This paper looks at the development of thick film hybrids and their relative position in the markets of the USA, Japan and Western Europe. Industry structure and the importance of in‐house manufacturing and development are discussed, together with future technical trends. Hybrids are viewed as one of a growing number of interconnection technologies available to the OEM, and no easing of substitution pressures is forecast. However, opportunities will continue to exist for this important technology, providing suppliers position themselves carefully in the market.

The purpose of this paper is to design and implement a fully integrated low‐phase noise and large tuning range dual‐band LC voltage‐controlled oscillator (VCO) in 0.13 μm complementary metal oxide semiconductor (CMOS) technology.

Two parallel‐connected single‐band VCOs are designed to implement the proposed VCO. Adopting a simple and straight‐forward architecture, the dual‐band VCO is configured to operate at two frequency bands, which are from 1.48 GHz to 1.78 GHz and from 2.08 GHz to 2.45 GHz. A band selection circuit is designed to perform band selection process based on the controlling input signal.

The proposed VCO features phase noise of −104.7 dBc/Hz and −108.8 dBc/Hz at 1 MHz offset frequency for both low corner and high corner end of the low‐band operation. For high‐band operation, phase‐noise performance of −101.1 dBc/Hz and −110.4 dBc/Hz at 1 MHz offset frequency are achieved. The measured output power of the dual‐band VCO ranges from −8.4 dBm to −5.8 dBm and from −9.6 dBm to −8.0 dBm for low‐band and high‐band operation, respectively. It was also observed that the power differences between the fundamental spectrum and the nearby spurious tone range from −67.5 dBc to −47.7 dBc.

The paper is useful to both the academic and industrial fields since it promotes the concept of multi‐band or multi‐standard system which is currently in demand in the telecommunication industry.

This paper explores the use of models of substrate behaviour to examine the wireability constraints on PCBs due to signal layers and buried and through vias. The importance of product scale as a factor affecting technology choice is examined in detail, and the factors that decide the need for multi‐layer construction and buried and through vias are discussed. Large PCB layouts are constrained by lack of space for traces ‐ trace bound; a limitation that can be removed by using multi‐layers and through hole vias. Small PCB layouts are constrained by lack of space for vias ‐ via bound; buried vias and landless vias are particularly useful for maximising wiring density under these conditions. A further observation is that the use of multiple layers offers diminishing returns as each further layer is added. For small high wiring density PCBs approximately four layers supporting blind vias can give excellent support for the use of high I/O (Input/Output) density packages.

The design and implementation of a broadband quasi-monolithic microwave integrated circuit (q-MMIC) power amplifier (PA) is presented for 0.2 to 2.2 GHz applications.

To obtain an efficient, high-gain and high-power performance with in a compact and low-cost size, the prototype is based on Gallium nitride (GaN) on SiC 0.25-µm transistors, whereas the passive matching networks are realized on an AlN substrate as thin film circuit.

Measured results of the q-MMIC PA across the 0.2 to 2.2 GHz band show at least 32 ± 3 dB small-signal gains, an output power of 7 to 12 W and an average power add efficiency greater than 54%. The q-MMIC occupies an area of 12.8 × 14.5 mm².

To the best of the authors’ knowledge, this work reports the first full integrated PA which covers the frequency range of 0.2 to 2.2 GHz and achieves the combination of highest gain, about 10 W output power, together with the smallest component size among all published GaN PAs to date.

This paper aims to review in-memory computing (IMC) for machine learning (ML) applications from history, architectures and options aspects. In this review, the authors investigate different architectural aspects and collect and provide our comparative evaluations.

Collecting over 40 IMC papers related to hardware design and optimization techniques of recent years, then classify them into three optimization option categories: optimization through graphic processing unit (GPU), optimization through reduced precision and optimization through hardware accelerator. Then, the authors brief those techniques in aspects such as what kind of data set it applied, how it is designed and what is the contribution of this design.

ML algorithms are potent tools accommodated on IMC architecture. Although general-purpose hardware (central processing units and GPUs) can supply explicit solutions, their energy efficiencies have limitations because of their excessive flexibility support. On the other hand, hardware accelerators (field programmable gate arrays and application-specific integrated circuits) win on the energy efficiency aspect, but individual accelerator often adapts exclusively to ax single ML approach (family). From a long hardware evolution perspective, hardware/software collaboration heterogeneity design from hybrid platforms is an option for the researcher.

IMC’s optimization enables high-speed processing, increases performance and analyzes massive volumes of data in real-time. This work reviews IMC and its evolution. Then, the authors categorize three optimization paths for the IMC architecture to improve performance metrics.

To characterise the optical performance of organic multi‐mode optical waveguides integrated with printed circuit board (PCB) and to demonstrate the feasibility of 2.5 and 10 Gbps optical interconnection in board‐level, respectively.

This paper provides both qualitative and quantitative approaches for the characterization the wave guide performance, i.e. using loss measurement, optical beam profiling, ethernet verification, and eye‐diagram testing. In addition to wave guide loss measurement, the most significance part of the work reported in this paper is to evaluate optical wave guides with coupled VCSELs, by which a 3 dB coupling design budget can thus be identified. Furthermore, by artificially manipulating coupling conditions, practical concerns of EOPCB integration, including waveguide geometry, VCSEL driving power, alignment tolerance, coupling spacing, etc. are studied.

Thermal stability studies related to PCB lamination processes show the feasibility of organic waveguides integrated to traditional PCB manufacturing. For a direct VCSEL/PD coupling scheme, a 3 dB power budget is experimentally identified. For short reach optical interconnection, 10 Gbps up to 17 cm propagation on PCB can be achieved by using 50×50 μm multi‐mode organic waveguides, where a±25 μm tolerance of optical alignment is compatible to the design rules of PCB.

The value of the paper lies in its systematic approaches to identify the waveguide performance through both qualitative and quantitative indices. The correlation between geometry design, processes, coupling conditions, and optical performance of organic waveguides explored in detail. Not only is a standard eye‐diagram test used to verify the waveguide at 2.5 and 10 Gbps bandwidth, but also a prototype of optical data‐communication on giga‐ethernet is demonstrated for long term stability. Following these analytical methods, readers can understand more about the optical performance of waveguides when designing optical interconnection for high speed electro‐optical integrated PCBs.