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This paper aims to address the various issues of board‐level (off‐chip) interconnects testing. A new algorithm based on the boundary scan architecture is developed to test off‐chip interconnect faults. The proposed algorithm can easily diagnose which two interconnects are shorted.

The problems in board‐level interconnects testing are not simple. A new algorithm is developed to rectify some of the problems in existing algorithms. The proposed algorithm to test board‐level interconnect faults is implemented using Verilog on Modelsim software. The output response of each shorting between different wires of different nodes is different, which is the basis of fault detection by the proposed algorithm. The test vectors are generated by the test pattern generator and these test vectors are different for different nodes. This work implements built in self test using boundary scan technique.

The dominant‐1 (wired‐OR, denoted as WOR), dominant‐0 (wired‐AND, denoted as WAND) and stuck‐at faults are tested using the proposed algorithm. The proposed algorithm is also compared with the several algorithms in the literature, i.e. modified counting, walking one's algorithm and others. This paper's results are found to be better than the existing algorithms.

The limitation of the proposed algorithm is that, at any time, the faults on any seven nodes can be tested to avoid aliasing. So, the groups are formed out of total nodes, in a multiple of seven to carry out the testing of faults.

The proposed algorithm is free from the problems of syndromes and utilizes a smaller number of test vectors.

Various existing algorithms namely modified counting, walking one's algorithm and others are discussed. A new algorithm is developed which can easily detect board‐level dominant‐1 (WOR), dominant‐0 (WAND) and stuck‐at faults. The proposed algorithm is completely free from aliasing and confounding syndromes.

This paper looks at the growth, current situation and future of the thick film hybrid industry worldwide. The approach taken has been to regard the thick film hybrid as primarily a sub‐assembly, both from a commercial and technical point of view. This helps to identify those major features that have shaped the industry and will influence its future.

As a result of reorganisation within the Company, AVX Limited have appointed Keith France as General Manager, Sales and Marketing. Previously General Manager, Sales, Europe, Mr France now assumes the added responsibility for the marketing of AVX products throughout Europe.

The coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB) materials causes a reliability issue for ball grid array type electronic packages. This makes it difficult for conventional wafer level chip scaled packaging (WLCSP) with large die to satisfy the reliability requirements. Therefore, in this study a novel solder joint protection‐WLCSP (SJP‐WLCSP) structure is proposed to overcome the reliability issue.

The SJP‐WLCSP makes use of a delaminating layer to reduce the problem of CTE mismatch. In the SJP‐WLCSP, a delaminating layer is interposed between the top layer of the chip and the bottom insulating layer of the redistribution copper metal traces. As a result, the stress on the solder joints can be released by allowing cracks to form in the delaminating layer.

To elucidate the thermo‐mechanical behaviour of tin‐lead eutectic solder joints and copper traces, a non‐linear analysis, based on a 3D finite element (FE) model, under accelerated thermal test loadings was carried out. The maximum equivalent stress/strain in the solder joints predicted by the FE simulation were found to diminish significantly when applying the delaminating layer. In addition, parametric FE analysis was also applied in this study, and based on the design concepts within this study, a robust novel SJP‐WLCSP could be achieved.

In this work, a new packaging concept with high reliability, low cost and easy fabrication was developed to reduce the shear stress in the solder joints due to the CTE mismatch between silicon chips and organic PCBs.

High Q on‐chip inductors and low loss on‐chip interconnects and transmission lines are an important roadblock for the further development of Si‐based technologies at RF and microwave frequencies. In this paper, inductors are realized on standard Si wafers (20 Ω.cm) using MCM‐D processing. This consists of realizing two low K dielectric layers (BCB) and a thick Cu interconnect layer. Inductors with 5 μm lines and spaces are demonstrated for a 5 μm thick Cu layer, hereby leading to a very compact and high performance inductors: Q‐factors in the range of 25 to 30 have been obtained for inductances in the range of 1 to 5 nH. It is also shown how the Q‐factor and resonance frequency vary as a function of the inductor layout parameters and the thickness of the BCB and Cu layers. The realized 50 Ω CPW lines (lateral dimension of 40 μm) have a measured loss of only 0.2 dB/mm at 25 GHz.

To review and explore optical fiber and carbon nanotube (CNT) as prospective alternatives to copper in VLSI interconnections.

As the technology moves to deep submicron level, the interconnect width also scales down. Increasing resistivity of copper with scaling and rising demands on current density drives the need for identifying new wiring solutions. This paper explores various alternatives to copper. Metallic CNTs, optical interconnects are promising candidates that can potentially address the challenges faced by copper.

Although, the theoretical aspects proves CNTs and optical interconnect to be better alternative against copper on the ground of performance parameters such as power dissipation, switching delay, crosstalk. But copper would last for coming decades on integration basis.

This paper reviews the state‐of‐the‐art in CNT interconnect and optical interconnect research; and discusses both the advantages and challenges of these emerging technologies.

A major limitation to achieving significant speed increases in VLSI lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of fifth generation supercomputing, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information between chips or between boards. As the on‐chip performance of VLSI continues to improve via the scale‐down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realised in reducing cross‐talk between the metallic routings, and the interconnects need no longer be constrained to the plane of the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.