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Article

E.C. Couble, O.B. Dutkewych, S.M. Florio, M.V. Marsh and R.F. Staniunas

The technological development and characteristics of an innovative process and composition for immersion plating and fusing of a solderable tin/lead deposit over copper…

Abstract

The technological development and characteristics of an innovative process and composition for immersion plating and fusing of a solderable tin/lead deposit over copper are discussed. The process offers a viable alternative to hot air solder levelling, electrodeposition/selective stripping, or inhibitor coatings for maintaining solderability of printed wiring boards. A flat, uniform solderable tin/lead coating on all feature surfaces and edges is achieved. A number of important benefits are derived. The ability to coat any copper surface uniformly, including fine pitch features, is substantially enhanced. Solderability is improved because of a thick, flat, co‐planar and uniform tin/lead deposit on all copper surfaces. Typical thickness and composition of the fused alloy are 150 to 300 microinches (4 to 8 microns) and 65 to 75% tin.

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Circuit World, vol. 19 no. 1
Type: Research Article
ISSN: 0305-6120

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Article

K. Minten and J. Cisson

This, the third in a series of papers, reports an investigation of the semi‐additive process strategies of PWB manufacture. It will show that, although the adoption of a…

Abstract

This, the third in a series of papers, reports an investigation of the semi‐additive process strategies of PWB manufacture. It will show that, although the adoption of a ‘naked’ palladium catalyst is the optimal production strategy in terms of cost, caution must be exercised in its implementation, particularly with regard to material process flow and solder mask type employed. It will be demonstrated that the use of a thin, sacrificial ‘flash’ of electroless copper prior to circuitisation and full build deposition will be required for the liquid photoimageable soldermask (LPISM) approach.

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Circuit World, vol. 19 no. 2
Type: Research Article
ISSN: 0305-6120

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Article

M.W. Gray

The possible causes of inner layer junction cracks on multilayer PCBs are discussed and the problems that cracks can cause under rework conditions. The procedure to…

Abstract

The possible causes of inner layer junction cracks on multilayer PCBs are discussed and the problems that cracks can cause under rework conditions. The procedure to identify the cracks and their exact location within and around the electroless copper junction is shown, along with guidelines on the possible ways to eliminate the cracking problem and on testing procedures to ensure a reliable product.

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Circuit World, vol. 15 no. 2
Type: Research Article
ISSN: 0305-6120

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Article

J. Cisson, J. Seigo and K. Minten

This paper constitutes a follow‐up to earlier work published in Circuit World, Vol. 17, No. 4. The first paper studied the metallographic structures of two commercially…

Abstract

This paper constitutes a follow‐up to earlier work published in Circuit World, Vol. 17, No. 4. The first paper studied the metallographic structures of two commercially available full build electroless copper foils. Part 2 reports the investigations carried out into the etching characteristics of these copper foils, chemically deposited from full build electroless copper baths designated high elongation (HE) and high strength (HS). It is shown that, although attention should be given to the choice of etchant for these copper foils, they do not exhibit an uncontrollable etch rate, as is often feared.

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Circuit World, vol. 18 no. 4
Type: Research Article
ISSN: 0305-6120

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Article

K. Minten and J. Toth

Two current full build electroless copper deposits were investigated. This paper demonstrates that there are fundamental differences in the nature of their deposits. The…

Abstract

Two current full build electroless copper deposits were investigated. This paper demonstrates that there are fundamental differences in the nature of their deposits. The consequences of these differences are highlighted for the PWB manufacturer.

Details

Circuit World, vol. 17 no. 4
Type: Research Article
ISSN: 0305-6120

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Article

K. Minten, K. Kitchens and J. Cisson

In the preceding three parts of this series, the authors have extensively reviewed and quantified the special processing sequences required for the ‘additive’ and…

Abstract

In the preceding three parts of this series, the authors have extensively reviewed and quantified the special processing sequences required for the ‘additive’ and ‘semi‐additive’ process strategies of PWB manufacture. In this, the fourth part of the series of five, they wish to present a series of full build processes which meet all the interconnect requirements of the 1990s while eliminating the drawbacks traditionally associated with additive processes.

Details

Circuit World, vol. 20 no. 3
Type: Research Article
ISSN: 0305-6120

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