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Article
Publication date: 18 October 2022

Nuha Rhaffor, Wei Keat Ang, Mohamed Fauzi Packeer Mohamed, Jagadheswaran Rajendran, Norlaili Mohd Noh, Mohd Tafir Mustaffa and Mohd Hendra Hairi

The purpose of this study is to show that due to the emergence of the Internet of Things (IoT) industry in recent years, the demand for the higher integration of wireless…

Abstract

Purpose

The purpose of this study is to show that due to the emergence of the Internet of Things (IoT) industry in recent years, the demand for the higher integration of wireless communication systems with a higher data rate of transmission capacity and lower power consumption has increased tremendously. The radio frequency power amplifier (PA) design is getting more challenging and crucial. A PA for a 2.45 GHz IoT application using 0.18 µm complementary metal oxide semiconductor (CMOS) technology is presented in this paper.

Design/methodology/approach

The design consists of two stages, the driver and output stage, where both use a single-stage common source transistor configuration. In view of performance, the PA can deliver more than 20 dB gain from 2.4 GHz to 2.5 GHz.

Findings

The maximum output power achieved by PA is 13.28 dBm. As the PA design is targeted for Bluetooth low energy (BLE) transmitter use, a minimum of 10 dBm output power should be achieved by PA to transmit the signal in BLE standard. The PA exhibits a constant output third-order interception point of 18 dBm before PA becomes saturated after 10 dBm output power. The PA shows a peak power added efficiency of 17.82% at the 13.24 dBm output power.

Originality/value

The PA design exhibits good linearity up to 10 dBm out the PA design exhibits good linearity up to 10 dBm output power without sacrificing efficiency. At the operating frequency of 2.45 GHz, the PA exhibits a stability k-factor, the value of more than 1; thus, the PA design is considered unconditional stable. Besides, the PA shows the s-parameters performance of –7.91 dB for S11, –11.07 dB for S22 and 21.5 dB for S21.

Details

Microelectronics International, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 22 February 2021

Selvakumar Mariappan, Jagadheswaran Rajendran, Norlaili Mohd Noh, Yusman Yusof and Narendra Kumar

The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity…

Abstract

Purpose

The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE).

Design/methodology/approach

The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3) to be canceled with the main PA’s fixed negative gm3. The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity.

Findings

For driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc.

Originality/value

In this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

Details

Circuit World, vol. 48 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

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