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The purpose of this paper is to design and construct an amplitude shift keying (ASK) modulator, which, using the digital binary modulating signal, controls a floating memristor emulator (MR) internally without the need for additional control circuits to achieve the ASK modulated wave.

A binary digital unipolar signal to be modulated is converted by a pre-processor circuit into a suitable bipolar modulating direct current (DC) signal for the control of the MR state, using current conveyors the carrier signal’s amplitude is varied with the change in the memristance of the floating MR. A high pass filter is then used to remove the DC control signal (modulating signal) leaving only the modulated carrier signal.

The results from the experiment and simulation are in agreement showed that the MR can be switched between two states and that a change in the carrier signals amplitude can be achieved by using an MR. Thus, showing that the circuit behavior is in line with the proposed theory and validating the said theory.

In this paper, the binary signal to be modulated is modified into a suitable control signal for the MR, thus the MR relies on the internal operation of the modulator circuit for the control of its memristance. An ASK modulation can then be achieved using a floating memristor without the need for additional circuits or signals to control its memristance.

Automatic modulation recognition (AMR) is a challenging problem in intelligent communication systems and has wide application prospects. At present, although many AMR methods based on deep learning have been proposed, the methods proposed by these works cannot be directly applied to the actual wireless communication scenario, because there are usually two kinds of dilemmas when recognizing the real modulated signal, namely, long sequence and noise. This paper aims to effectively process in-phase quadrature (IQ) sequences of very long signals interfered by noise.

This paper proposes a general model for a modulation classifier based on a two-layer nested structure of long short-term memory (LSTM) networks, called a two-layer nested structure (TLN)-LSTM, which exploits the time sensitivity of LSTM and the ability of the nested network structure to extract more features, and can achieve effective processing of ultra-long signal IQ sequences collected from real wireless communication scenarios that are interfered by noise.

Experimental results show that our proposed model has higher recognition accuracy for five types of modulation signals, including amplitude modulation, frequency modulation, gaussian minimum shift keying, quadrature phase shift keying and differential quadrature phase shift keying, collected from real wireless communication scenarios. The overall classification accuracy of the proposed model for these signals can reach 73.11%, compared with 40.84% for the baseline model. Moreover, this model can also achieve high classification performance for analog signals with the same modulation method in the public data set HKDD_AMC36.

At present, although many AMR methods based on deep learning have been proposed, these works are based on the model’s classification results of various modulated signals in the AMR public data set to evaluate the signal recognition performance of the proposed method rather than collecting real modulated signals for identification in actual wireless communication scenarios. The methods proposed in these works cannot be directly applied to actual wireless communication scenarios. Therefore, this paper proposes a new AMR method, dedicated to the effective processing of the collected ultra-long signal IQ sequences that are interfered by noise.

The purpose of this paper is to present a novel image‐labeling CMOS sensor for modulated marker detection.

An image scene with multiple objects, each identified by a flashing light‐emitting diode (LED), is captured by the sensor. The LED's frequency is a representation of the object ID‐tag. The sensor detects and labels the objects by identifying the signal frequencies. The processing is performed in‐pixel and, since the object detection task is simplified, power dissipation is reduced. A 64×64 pixel sensor is designed in the 0.6 μm CMOS technology.

Simulation results show successful object identification. At a frame rate of 250 fps the measured power consumption is 11 mW, which is less than those of the previously reported object detection solutions. The application of the presented sensor is shown in several different robotic fields such as unmanned aerial vehicles (UAVs) vision, household robots and industrial robots. It is also explained how the sensor can be used for low‐power localization and position detection of the robot vehicles.

The paper shows that the sensor is a suitable solution for low‐power landmark detection and robot localization.

This paper aims to propose the modeling of nanostructured memristor, and the circuit of amplitude modulator was designed and analyzed with memristor. The simulation results show that the nanostructured memristor can be utilized to implement the desired amplitude modulated signal.

The modeling of nanostructured memristor is proposed in this paper, and the circuit of amplitude modulator was designed and analyzed with memristor, amplifiers and BPF device. For measuring the modulated signal, the emulator circuit of memristor is designed. The simulation results show that the nanostructured memristor can be utilized to implement the desired amplitude modulated signal.

The innovations of this work are as follows: the AM modulator circuit using memristor has been proposed, analyzed and simulated. The emulator of memristor is given.

The innovations of this work are as follows: the AM modulator circuit using memristor has been proposed, analyzed and simulated. The emulator of memristor is given, and the results of this work demonstrate that the nonlinearity of the memristor can be used to generate the desired amplitude modulation free of harmonic sidebands, because of distortion of the modulating signal.

This paper aims to explore a new approach for time-domain modelling of interconnects with highly oscillatory modulated sources.

The paper uses an asymptotic method in conjunction with the Green’s function of the telegrapher’s equations. The Green’s function is expressed as a series of rational functions in the Laplace domain and are converted to pole-residue form, thereby enabling time-domain implementation.

The results indicate that the method is accurate for modelling interconnects when wide-varying frequencies are present in the sources.

The technique is important in circuit design for assessing signal integrity and in electromagnetic compatibility testing.

This paper aims to the increasing need for high-speed low-power data transmissions over frequency-selective fading channels has drawn attention to suggest dual-carrier modulation (DCM) for multiband orthogonal frequency division multiplexing (OFDM) transceivers for ultra wideband (UWB) wireless personal area network (WPAN).

Under frequency-selective fading channel conditions, the decoder is not sufficient enough to decode the transmission bits of severely attenuated data tones. Hence, the authors suggest DCM for a multiband OFDM transceiver because of its multiple capability of providing both frequency diversity and coding gain. It also resulted in low bit-error-rate (BER) at a given signal- to-noise ratio when compared to conventional multiband OFDM system. To achieve an optimised BER, DCM transforms four re-ordered bits into two quaternary phase shift keying symbols and further transforms to two 16-quadrature amplitude modulation-like (16-QAM) symbols with a suitable mapping technique, and at the receiver end, they are decoded with maximum likelihood decision rule. After performing the transformation, the outage probability and average BER expressions are derived to analyse the system performance.

DCM is suitable for high data rate transmission and is immune to frequency-selective fading. The outage and BER performance outstands over conventional multiband OFDM transceiver because of the inclusion of DCM mapping.

It is widely used in WPANs such as high definition multimedia interface and wireless universal serial bus.

This paper derives novel closed-form outage probability and a tight upper bound on average BER expressions for DCM-based multiband OFDM UWB transceiver over frequency-selective Nakagami-m fading channels for any arbitrary value of m. For this, moment-generating function of sum of squared, independent and identically distributed (i.i.d.) Nakagami-m random variables are used. Further, the system performance is also validated for the case of exponential decaying power delay profile, and the simulation results are provided to check the accuracy of the derived expressions.

The digital down converter (DDC) is a principal component in modern communication systems. The DDC process traditionally entails quadrature down conversion, bandwidth reducing filters and commensurate sample rate reduction. To avoid group delay, distortion linear phase FIR filters are used in the DDC. The filter performance specifications related to deep stopband attenuation, small in-band ripple and narrow transition bandwidth lead to filters with a large number of coefficients. To reduce the computational workload of the filtering process, filtering is often performed as a two-stage process, the first stage being a down sampling Hoegenauer (or cascade-integrated comb) filter and a reduced sample rate FIR filter. An alternative option is an M-Path polyphase partition of a band cantered FIR filter. Even though IIR filters offer reduced workload to implement a specific filtering task, the authors avoid using them because of their poor group delay characteristics. This paper aims to propose the design of M-path, approximately linear phase IIR filters as an alternative option to the M-path FIR filter.

Two filter designs are presented in the paper. The first approach uses linear phase IIR low pass structure to reduce the filter’s coefficient. Whereas the second approach uses multipath polyphase structure to design approximately linear phase IIR filter in DDC.

The authors have compared the performance and workload of the proposed polyphase structured IIR filters with state-of-the-art filter design used in DDC. The proposed design is seen to satisfy tight design specification with a significant reduction in arithmetic operations and required power consumption.

The proposed design is an alternate solution to the M-path polyphase FIR filter offering very less number of coefficients in the filter design. Proposed DDC using polyphase structured IIR filter satisfies the requirement of linear phase with the least number of computation cost in comparison with other DDC structure.