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Article
Publication date: 19 June 2017

Mehdi Habibi, Mohammad Shakarami and Ali Asghar Khoddami

Sensor networks have found wide applications in the monitoring of environmental events such as temperature, earthquakes, fire and pollution. A major challenge with sensor…

Abstract

Purpose

Sensor networks have found wide applications in the monitoring of environmental events such as temperature, earthquakes, fire and pollution. A major challenge with sensor network hardware is their limited available energy resource, which makes the low power design of these sensors important. This paper aims to present a low power sensor which can detect sound waveform signatures.

Design/methodology/approach

A novel mixed signal hardware is presented to correlate the received sound signal with a specific sound signal template. The architecture uses pulse width modulation and a single bit digital delay line to propagate the input signal over time and analog current multiplier units to perform template matching with low power usage.

Findings

The proposed method is evaluated for a chainsaw signature detection application in forest environments, under different supply voltage values, input signal quantization levels and also different template sample points. It is observed that an appropriate combination of these parameters can optimize the power and accuracy of the presented method.

Originality/value

The proposed mixed signal architecture allows voltage and power reduction compared with conventional methods. A network of these sensors can be used to detect sound signatures in energy limited environments. Such applications can be found in the detection of chainsaw and gunshot sounds in forests to prevent illegal logging and hunting activities.

Details

Sensor Review, vol. 37 no. 3
Type: Research Article
ISSN: 0260-2288

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Article
Publication date: 7 June 2021

Jincan Zhang, Min Liu, Jinchan Wang and Kun Xu

High-speed Indium Phosphide (InP) HBTs have been widely used to design high-speed analog, digital and mixed-signal integrated circuits. The purpose of this study is to…

Abstract

Purpose

High-speed Indium Phosphide (InP) HBTs have been widely used to design high-speed analog, digital and mixed-signal integrated circuits. The purpose of this study is to propose a new parameter extraction procedure for determining an improved T-topology small-signal equivalent circuit of InP heterojunction bipolar transistors (HBTs).

Design/methodology/approach

The alternating current crowding effect is considered through adding the intrinsic base capacitance in the small-signal equivalent circuit. All of the circuit parameters are extracted directly without using any approximation.

Findings

The extraction technique is more easily understood and clearer than other extraction methods, as the equations are derived from the S-parameters by peeling peripheral elements from small-signal models to get reduced ones and extracting each equivalent-circuit parameter using each equation.

Originality/value

To validate the presented parameter extraction technology, an n-p-n emitter-up InP HBT was analyzed adopting the method. Excellent agreement between measured and modeled S-parameters is obtained up to 40 GHz.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

Keywords

Abstract

Details

Microelectronics International, vol. 26 no. 2
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 1 December 2004

K. Arshak, E. Jafer, G. Lyons, D. Morris and O. Korostynska

The development of a sensor microsystems containing all the components of data acquisition system, such as sensors, signal‐conditioning circuits, analog‐digital converter…

Abstract

The development of a sensor microsystems containing all the components of data acquisition system, such as sensors, signal‐conditioning circuits, analog‐digital converter, interface circuits and embedded microcontroller (MCU), has become the focus of attention in many biomedical applications. A review of the microsystems technology is presented in this paper, along with a discussion of the recent trends and challenges associated with its developments. A basic description of each sub‐system is also given. This includes the different front end, mixed analog‐digital, power management, and radio transmitter‐receiver circuits. These sub‐system designs are presented and discussed in a comparative study and final remarks are made. The performance of each sub‐system is assessed regarding many aspects related to the overall system performance.

Details

Microelectronics International, vol. 21 no. 3
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 14 August 2020

Vaithiyanathan D., Megha Singh Kurmi, Alok Kumar Mishra and Britto Pari J.

In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high…

Abstract

Purpose

In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications.

Design/methodology/approach

The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit.

Findings

The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased.

Originality/value

The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

Details

World Journal of Engineering, vol. 17 no. 6
Type: Research Article
ISSN: 1708-5284

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Article
Publication date: 12 July 2011

Stefan Ludwig and Wolfgang Mathis

This paper aims to present a method for the efficient reduction of networks modelling parasitic couplings in very‐large‐scale integration (VLSI) circuits.

Abstract

Purpose

This paper aims to present a method for the efficient reduction of networks modelling parasitic couplings in very‐large‐scale integration (VLSI) circuits.

Design/methodology/approach

The parasitic effects are modelled by large RLC networks and current sources for the digital switching currents. Based on the determined behaviour of the digital modules, an efficient description of these networks is proposed, which allows for a more efficient model reduction than standard methods.

Findings

The proposed method enables a fast and efficient simulation of the parasitic effects. Additionally, an extension of the reduction method to elements, which incorporate some supply voltage dependence to model the internal currents more precisely than independent current sources is presented.

Practical implications

The presented method can be applied to large electrical networks, used in the modelling of parasitic effects, for reducing their size. A reduced model is created which can be used in investigations with circuit simulators requiring a lowered computational effort.

Originality/value

Contrary to existing methods, the presented method includes the knowledge of the behaviour of the sources in the model to enhance the model reduction process.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 30 no. 4
Type: Research Article
ISSN: 0332-1649

Keywords

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Article
Publication date: 24 April 2007

Radhalakshmi Ramakrishnan and Maqsood A. Chaudhry

This paper aims to present a design of a single power supply, low voltage (1.2) high performance operational amplifier using 0.13 μm technology whose characteristics are…

Abstract

Purpose

This paper aims to present a design of a single power supply, low voltage (1.2) high performance operational amplifier using 0.13 μm technology whose characteristics are superior compared to the other designs available in the literature.

Design/methodology/approach

The authors set out to design an operational amplifier whose characteristics will be superior to the current available designs in the literature. Because of potential applications, a single 1.2 V supply was used. The layout was obtained using Microwind 0.13 μm technology. The design was tested using PSPICE Version 10.0. Various amplifier parameters were obtained and are compared with the other single supply, low voltage amplifiers available in the literature.

Findings

The presented amplifier has better characteristics such as open loop gain, power supply rejection ratio, common mode rejection ratio, etc.

Practical implications

Since, 0.13 μm, 1.2 V technology has become standard in digital VLSI design, there is a great need for high performance operational amplifiers that operate off of 1.2 V for mixed signal applications in such areas as mobile phones.

Originality/value

The presented amplifier has better characteristics compared to few 1.2 V supply voltage amplifiers available in the literature.

Details

Microelectronics International, vol. 24 no. 2
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 16 June 2021

Kulbhushan Sharma, Anisha Pathania, Jaya Madan, Rahul Pandey and Rajnish Sharma

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide…

Abstract

Purpose

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

Design/methodology/approach

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

Findings

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Research limitations/implications

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

Social implications

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

Originality/value

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

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Article
Publication date: 1 December 2003

H. Ymeri, B. Nauwelaers, K. Maex and D. De Roest

New analytical approximation for the frequency‐dependent impedance matrix components of symmetric VLSI interconnect on lossy silicon substrate are derived. The results…

Abstract

New analytical approximation for the frequency‐dependent impedance matrix components of symmetric VLSI interconnect on lossy silicon substrate are derived. The results have been obtained by using an approximate quasi‐magnetostatic analysis of symmetric coupled microstrip on‐chip interconnects on silicon. We assume that the magnetostatic field meets the boundary conditions of a single isolated infinite line; therefore, the boundary conditions for the conductors in the structure are approximately satisfied. The derivation is based on the approximate solution of quasi‐magnetostatic equations in the structure (dielectric and silicon semi‐space), and takes into account the substrate skin‐effect. Comparisons with published data from circuit modeling or full‐wave numerical analyses are presented to validate the inductance and resistance expressions derived for symmetric coupled VLSI interconnects. The analytical characterization presented in this paper is well situated for inclusion into CAD codes in the design of RF and mixedsignal integrated circuits on silicon.

Details

Microelectronics International, vol. 20 no. 3
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 27 March 2009

Christine Connolly

The purpose of this paper is to explore progress in electronic circuit miniaturisation, and study the new medical sensor devices emerging.

Abstract

Purpose

The purpose of this paper is to explore progress in electronic circuit miniaturisation, and study the new medical sensor devices emerging.

Design/methodology/approach

Circuit packaging advances in the mobile phone sector are examined. The products and expertise of a leading producer of non‐contact sensors and medical implants are described, followed by a series of medical applications of 3D circuitry.

Findings

Mobile phone enhancements are driving innovations in electronics that are transferable to other industries. Wafer‐thinning and 3D interconnection techniques shrink complex circuitry, enabling the construction of sensitive intelligent wireless sensors. Biologically inert packaging enables such devices to be implanted in the human body to improve sight and hearing, and monitor bone‐healing after surgery.

Originality/value

The paper shows how electronic packaging innovations are spinning out into non‐contact sensors and medical implants and will be of interest to engineers in these fields, and of general interest to a wider readership.

Details

Sensor Review, vol. 29 no. 2
Type: Research Article
ISSN: 0260-2288

Keywords

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