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This paper seeks to review recent advances in wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging.

Of the 91 journal papers, 59 were published in 2005‐2007 and topics related to wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging are reviewed.

Research on advanced wire bonding is continuously performed for advanced and complex applications such as stacked‐dies wire bonding, wire bonding of low‐k ultra‐fine‐pitch devices, and copper wire bonding. Owing to its many advantages, flip chip using adhesive has gained more popularity. Research on the reliability of lead‐free solder joints is being conducted world‐wide. The new challenges, solutions and new developments are discussed in this paper.

Because of page limitation of this review paper and the large number of the journal papers available, only a brief review is conducted. Further reading is needed for more details.

This review paper attempts to provide introduction to recent developments and the trends in terms of the topics for advanced microelectronics packaging. With the references provided, readers may explore more deeply, focusing on a particular issue.

Alan Hobby has recently been appointed Applications Engineer at DEK Printing Machines Ltd, Weymouth. In 1968 he joined Ferranti at Bracknell and became one of the small team setting up the thick film production unit. Four years later he joined EMI at Hayes as the Production Engineer, where he gained experience in the manufacture of high volume but relatively simple hybrids. In 1975 Alan moved to Marconi Electronic Devices Ltd at Portsmouth, where he was one of the engineers responsible for the company's programme of qualification as a hybrid manufacturer for the European Space Agency and for their BS 9450 approval programme. Since then he has been concerned with the development of printing and firing techniques both at Portsmouth and at Marconi's high volume production unit at Swindon.

This paper attempts to review recent advances in wire bonding using insulated wire and new challenges in wire bonding for advanced microelectronics packaging.

Dozens of journal articles, conference articles and patents published or issued in 2004‐2007 are reviewed.

The advantages and problems/challenges related to wire bonding using insulated wire are briefly analysed, and several solutions to the problems and recent findings/developments related to wire bonding using insulated wire are discussed.

Because of page limitation of the paper, only brief review is conducted. Further reading is needed for more details.

This paper attempts to provide introduction to recent developments and the trends in wire bonding using insulated wire. With the references provided, readers may explore more deeply by reading the original articles and patent documents.

The advent of novel advanced packaging technologies such as multilayer thin‐film interconnect, combined with continuous improvements in IC clock speed and circuit performance, has placed extreme demands on electronics packaging and package materials. Aluminium nitride (AIN) ceramic offers significant opportunities and advantages for package design, particularly where the effective thermal management and overall reliability of large devices are a high priority. AIN has already been successfully employed at the substrate level for the enhanced thermal relief of power devices. Examples of these applications include heat sinks and device mounts for thyristor modules, power transistors, solid state relays, power SCRs, switching modules, LEDs and various RF package configurations. Both bare and metallised AIN substrates are beginning to find application as a substitute for beryllia (BeO) in mass market and high reliability automotive electronics applications. Successfully implementing AIN in a high level electronics packaging application requires a systems approach in which the intrinsic properties of AIN are considered as ‘first principles’ in shaping the package design process. The unique physicochemical and mechanical properties of AIN require the development of specialised metallisation and co‐firing processes to fabricate the advanced components necessary for hermetic packaging of complex devices and multichip modules. This paper presents a practical and mass manufacturable AIN‐based package tailored to these high level applications. The package design is unique in that it provides for the total separation of the electrical‐signal conduction from the mechanical support/mounting functions of the package. Such a separation of the functions improves both the package durability and reliability relative to currently available electronics packages of conventional designs.

Anicon, Inc. have recently appointed Friedrich Weiler as Managing Director, Anicon Europa, GmbH, and have announced the opening of Anicon's European headquarters facility in Munich.

The purpose of this paper is to review recent advances in wire bonding of low‐k devices.

Dozens of journal and conference articles published in 2005‐2008 are reviewed.

The paper finds that many articles have discussed and analysed problems/challenges such as bond pad metal peeling/lift, non‐sticking on pad, decreased bonding strength and lower wire‐bond assembly yield. The paper discusses the articles' solutions to the problems and recent findings/developments in wire bonding of low‐k devices.

Because of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.

The paper attempts to provide an introduction to recent developments and the trends in wire bonding of low‐k devices. With the references provided, readers may explore more deeply by reading the original articles.

I was an invited speaker to the ISHM‐Benelux meeting. As I arrived early, I also sat in on the committee meeting as an observer. Jos B. Peeters was the outgoing president and the incoming committee was widened to about 15 members compared with the previous 6. Following the unanimous election of all those nominated, the committee reconvened and elected Mr Kwikkers as the new president of ISHM‐Benelux. He is a professor at the Technische Hogeschole in Delft.

This paper aims to review recent advances and applications of abrasive processes for microelectronics fabrications.

More than 80 patents and journal and conference articles published recently are reviewed. The topics covered are chemical mechanical polishing (CMP) for semiconductor devices, key/additional process conditions for CMP, and polishing and grinding for microelectronics fabrications and fan-out wafer level packages (FOWLPs).

Many reviewed articles reported advanced CMP for semiconductor device fabrications and innovative research studies on CMP slurry and abrasives. The surface finish, sub-surface damage and the strength of wafers are important issues. The defects on wafer surfaces induced by grinding/polishing would affect the stability of diced ultra-thin chips. Fracture strengths of wafers are dependent on the damage structure induced during dicing or grinding. Different thinning processes can reduce or enhance the fracture strength of wafers. In the FOWLP technology, grinding or CMP is conducted at several key steps. Challenges come from back-grinding and the wafer warpage. As the Si chips of the over-molded FOWLPs are very thin, wafer grinding becomes critical. The strength of the FOWLPs is significantly affected by grinding.

This paper attempts to provide an introduction to recent developments and the trends in abrasive processes for microelectronics manufacturing. With the references provided, readers may explore more deeply by reading the original articles. Original suggestions for future research work are also provided.

The challenge presented by advanced package development in the past five years has further accentuated the constant need for package quality and reliability monitoring through extensive laboratory testing and evaluation. As pin counts and chip geometries have continued to increase, there has been additional pressure from the military and commercial sectors to improve interconnect designs for packaged chips, including chips directly attached to the printed wiring board (PWB). One of the options employed has been tape automated bonding (TAB). However, this assembly technique also presents new standardisation, qualification and reliability problems. Therefore, at Rome Air Development Center (RADC), there is regular assessment (through in‐house failure analysis studies) of parts destined for military and space systems. In addition, Department of Defense (DoD) high tech development programmes, such as very high speed integrated circuits (VHSIC), have utilised all present screening methods for package evaluation, and have addressed the need for development of more definitive non‐destructive tests. To answer this need, two RADC contractual efforts were awarded on laser thermal and ultrasonic inspection techniques. Through these package evaluations, a number of potential reliability problems are identified and the results provided to the specific contractors for corrective action implementation. Typical problems uncovered are lid material and pin corrosion, damage to external components and adhesion problems between copper leads and polyimide supports, hermeticity failures, high moisture content in sealed packages and particle impact noise detection (PIND) test failures (internal particles). Further tests uncover bond strength failures, bond placement irregularities, voids in die attach material (potential heat dissipation problems), and die surface defects such as scratches and cracks. This presentation will review the specific package level physical test methods that are employed as a means of evaluating reliable package performance. Many of the tests, especially the environmental tests—e.g., salt atmosphere and moisture resistance—provide accelerated forms of anticipated conditions and are therefore applied as destructive tests to assess package quality and reliability in field use. In addition to a manufacturer's compliance with designated qualification procedures, the key to package quality lies in utilising good materials and well‐controlled assembly techniques. This practice, along with effective package screen tests, will ensure reliable operation of very large scale integration (VLSI) devices in severe military and commercial environment applications.