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The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors.

This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-sensing circuitry has been designed using 5-μm CMOS technology. The pressure-sensing structure consists of three identical 10-μm-long and 50-μm-wide n-channel MOSFETs connected in current mirror configuration, with its input transistor as a reference MOSFET and output transistors are the pressure-sensing MOSFETs embedded at the centre and near the fixed edge of a silicon diaphragm measuring 100 × 100 × 2.5 μm. This arrangement of MOSFETs enables the sensor to sense tensile and compressive stresses, developed in the diaphragm under externally applied pressure, with respect to the input reference transistor of the mirror circuit. An analytical model describing the complete behaviour of the integrated pressure sensor has been described. The simulation results of the pressure sensor show high pressure sensitivity and a good agreement with the theoretical model has been observed. A five mask level process flow for the fabrication of the current mirror-sensing-based pressure sensor has also been described. An n-channel MOSFET with aluminium gate was fabricated to verify the fabrication process and obtain its electrical characteristics using process and device simulation software. In addition, an aluminium gate metal-oxide semiconductor (MOS) capacitor was fabricated on a two-inch p-type silicon wafer and its CV characteristic curve was also measured experimentally. Finally, the paper presents a comparative study between the current mirror pressure-sensing circuit with the traditional Wheatstone bridge.

The simulated sensitivities of the pressure-sensing MOSFETs of the current mirror-integrated pressure sensor have been found to be approximately 375 and 410 mV/MPa with respect to the reference transistor, and approximately 785 mV/MPa with respect to each other. The highest pressure sensitivities of a quarter, half and full Wheatstone bridge circuits were found to be approximately 183, 366 and 738 mV/MPa, respectively. These results clearly show that the current mirror pressure-sensing circuit is comparable and better than the traditional Wheatstone bridge circuits.

The concept of using a basic current mirror circuit for sensing tensile and compressive stresses developed in micro-mechanical structures is new, fully compatible to standard CMOS processes and has a promising application in the development of miniaturized integrated micro-sensors and sensor arrays for automobile, medical and industrial applications.

This paper aims to characterize the relationship between the interelectrode capacitance (C) of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the applied bias voltage (V) by a fractional-order equivalent model.

A Riemann–Liouville-type fractional-order equivalent model is proposed for the C–V characteristic of MOSFETs, which is based on the mathematical relationship between fractional calculus and the semiconductor physical model for the interelectrode capacitance of metal oxide semiconductor structure. The C–V characteristic data of an N-channel MOSFET are obtained by Silvaco TCAD simulation. A differential evolution-based offline scheme is exploited for the parameter identification of the proposed model.

According to the results of theoretical analysis, mathematical derivation, simulation and comparison, this paper illustrates that, along with the variation of bias voltage applied, the interelectrode capacitance (C) of MOSFETs performs a fractional-order characteristic.

This work uncovers the fractional-order characteristic of MOSFETs’ interelectrode capacitance. By the proposed model, the influence of doping concentration on the gate leakage parasitic capacitance of MOSFETs can be revealed. In the pre-defined doping concentration range, the relative error of the proposed model is less than 5% for the description of C–V characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs). Compared to some existing models, the proposed model has advantages in both model accuracy and model complexity, and the variation of model parameters can directly reflect the relationship between the characteristics of MOSFETs and the doping concentration of materials. Accordingly, the proposed model can be used for the microcosmic mechanism analysis of MOSFETs. The results of the analysis produce evidence for the widespread existence of fractional-order characteristics in the physical world.

This paper aims to describe the fabrication, packaging and testing of a resistive loaded p-channel metal-oxide-semiconductor field-effect transistor-based (MOSFET-based) current mirror-integrated pressure transducer.

Using the concept of piezoresistive effect in a MOSFET, three identical p-channel MOSFETs connected in current mirror configuration have been designed and fabricated using the standard polysilicon gate process and microelectromechanical system (MEMS) techniques for pressure sensing application. The channel length and width of the p-channel MOSFETs are 100 µm and 500 µm, respectively. The MOSFET M1 of the current mirror is the reference transistor that acts as the constant current source. MOSFETs M2 and M3 are the pressure-sensing transistors embedded on the diaphragm near the mid of fixed edge and at the center of the square diaphragm, respectively, to experience both the tensile and compressive stress developed due to externally applied input pressure. A flexible square diaphragm having a length of approximately 1,000 µm and thickness of 50 µm has been realized using deep-reactive ion etching of silicon on the backside of the wafer. Then, the fabricated sensor chip has been diced and mounted on a TO8 header for the testing with pressure.

The experimental result of the pressure sensor chip shows a sensitivity of approximately 0.2162 mV/psi (31.35 mV/MPa) for an input pressure of 0-100 psi. The output response shows a good linearity and very low-pressure hysteresis. In addition, the pressure-sensing structure has been simulated using the parameters of the fabricated pressure sensor and from the simulation result a pressure sensitivity of approximately 0.2283 mV/psi (33.11 mV/MPa) has been observed for input pressure ranging from 0 to 100 psi with a step size of 10 psi. The simulated and experimentally tested pressure sensitivities of the pressure sensor are in close agreement with each other.

This current mirror readout circuit-based MEMS pressure sensor is new and fully compatible to standard CMOS processes and has a promising application in the development CMOS-MEMS-integrated smart sensors.

Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels.

The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented.

The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%.

The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

This paper aims to describe the fabrication and characterization of current mirror-integrated microelectromechanical systems (MEMS)-based pressure sensor.

The integrated pressure-sensing structure consists of three identical 100-µm long and 500-µm wide n-channel MOSFETs connected in a resistive loaded current mirror configuration. The input transistor of the mirror acts as a constant current source MOSFET and the output transistors are the stress sensing MOSFETs embedded near the fixed edge and at the center of a square silicon diaphragm to sense tensile and compressive stresses, respectively, developed under applied pressure. The current mirror circuit was fabricated using standard polysilicon gate complementary metal oxide semiconductor (CMOS) technology on the front side of the silicon wafer and the flexible pressure sensing square silicon diaphragm, with a length of 1,050 µm and width of 88 µm, was formed by bulk micromachining process using tetramethylammonium hydroxide solution on the backside of the wafer. The pressure is monitored by the acquisition of drain voltages of the pressure sensing MOSFETs placed near the fixed edge and at the center of the diaphragm.

The current mirror-integrated pressure sensor was successfully fabricated and tested using in-house developed pressure measurement system. The pressure sensitivity of the tested sensor was found to be approximately 0.3 mV/psi (or 44.6 mV/MPa) for pressure range of 0 to 100 psi. In addition, the pressure sensor was also simulated using Intellisuite MEMS Software and simulated pressure sensitivity of the sensor was found to be approximately 53.6 mV/MPa. The simulated and measured pressure sensitivities of the pressure sensor are in close agreement.

The work reported in this paper validates the use of MOSFETs connected in current mirror configuration for the measurement of tensile and compressive stresses developed in a silicon diaphragm under applied pressure. This current mirror readout circuitry integrated with MEMS pressure-sensing structure is new and fully compatible to standard CMOS processes and has a promising application in the development CMOS-MEMS-integrated smart sensors.

The purpose of this paper is to present a comprehensive review on development and future trends in zinc oxide thin film transistors (ZnO TFTs). This paper presents the development of TFT technology starting from amorphous silicon, poly-Si to ZnO TFTs. This paper also discusses about transport and device modeling of ZnO TFT and provides a comparative analysis with other TFTs on the basis of performance parameters.

It highlights the need of high–k dielectrics for low leakage and low threshold voltage in ZnO TFTs. This paper also explains the effect of grain boundaries, trap densities and threshold voltage shift on the performance of ZnO TFT. Moreover, it also addresses the challenges like requirement of stable p-type ZnO semiconductor for various electronic applications and high value of ZnO mobility to meet growing demand of high-definition light emitting diode TV (HD-LED TV).

This review will motivate the readers to further investigate the conduction mechanism, best alternate for gate-dielectric and the deposition technique optimization for the enhancement of the performance of ZnO TFTs.

This is a literature review. The technological evolution of TFT in general and ZnO TFT in particular is presented in this paper.

The purpose of this paper is to study the effects of positive and negative bias stressing on switching performance of power VDMOSFETs used in communication systems.

A positive and a negative high‐field stress are applied on the gate oxide of MOS devices and electrical characterization is performed after each period of stress, a comparison is presented.

Compared results between the two types of stress show that certain doses of stress can increase the device speed. The underlying changes of the threshold voltage under these two types of stress are referred to as the variation of the gate oxide‐trapped charge and interface trap densities.

This paper presents new and original experiments run over a number of metal‐oxide semiconductor field effect transistor devices to compare the effects of the direction of the applied field on the degradation and the reliability of these structures.

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells.

This study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue.

The GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart.

Nano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit.

GNRFET devices are suitable for implementing low power and high density SRAM cell.

The conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices.

This paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

This study aims to present a mathematical method based on Poisson’s equation to calculate the voltage and volume charge density formed in the substrate under the floating gate area of a multiple-input floating-gate metal-oxide semiconductor metal-oxide semiconductor (MOS) transistor.

Based on this method, the authors calculate electric fields and electric potentials from the charges generated when voltages are applied to the control gates (CG). This technique allows us to consider cases when the floating gate has any trapped charge generated during the manufacturing process. Moreover, the authors introduce a mathematical function to describe the potential behavior through the substrate. From the resultant electric field, the authors compute the volume charge density at different depths.

The authors generate some three-dimensional graphics to show the volume charge density behavior, which allows us to predict regions in which the volume charge density tends to increase. This will be determined by the voltages on terminals, which reveal the relationship between CG and volume charge density and will allow us to analyze some superior-order phenomena.

The procedure presented here and based on coordinates has not been reported before, and it is an aid to generate a model of the device and to build simulation tools in an analog design environment.