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This paper aims to investigate the gas-sensing capability of Pd/TiO₂/Si MIS capacitor using capacitance versus gate voltage (C-V) response as a function of hydrogen gas concentration varying from 0.1 to 2 ppm at 300 kHz frequency.

The objective is to fabricate a metal–insulator–semiconductor (MIS) capacitor sensor based on TiO₂-thin-film insulator deposited by sol-gel spin-coating process. Gas-sensing signal derived on exposure to hydrogen with concentration varying from 0.1 to 2 ppm at different operating temperatures (room temperature to 1,500°C) was measured as variation in flat-band voltage in C-V characteristics of the MIS capacitor.

High sensitivity of the sensor is attributed to the large change of interface state charges because of the large surface-to-volume ratio of the nano-structured TiO₂. The values of response time as well as the recovery time have also been estimated and are found to be comparable to that observed in the case of conventional Metal Oxide Semiconductor (MOS) structure.

The use of Si substrate restricts the performance of gas sensors to 200°C, as the Si substrate begins to show conductive nature.

This paper deals with an MIS capacitor gas sensor which replaces conventional insulating material by TiO₂ and uses a high-quality fabrication procedure for controlled growth of novel surface structure.

Al₂O₃ used as gate dielectric enables exploitation of higher electric field capacity of SiC, improving capacitive coupling and memory retention in flash memories. Passivation of traps at interface and in bulk which causes serious threat is necessary for better performance. The purpose of this paper is to investigate the effect of post-deposition rapid thermal annealing (PDA) and post-metallization annealing (PMA) on the structural and electrical characteristics of Pd/Al2O3/6H-SiC capacitors.

Al₂O₃ film is deposited by ALD; PDA is performed by rapid thermal annealing (RTA) in N₂ at 900°C for 1 min and PMA in forming gas for 10 and 40 min. X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) measurements data are studied in addition to capacitance-voltage (C-V) and current-voltage (I-V) characteristics for the fabricated Pd/Al₂O₃/SiC capacitors. Conduction mechanism contributing to the gate leakage current is extracted for the entire range of gate electric field.

RTA forms aluminum silicide at the interface causing an increase in the density of the interface states and gate leakage current for devices with an annealed film, when compared with an as-deposited film. One order improvement in leakage current has been observed for the devices with RTA, after subjecting to PMA for 40 min, compared with those devices for which PMA was carried out for 10 min. Whereas, no improvement in leakage current has been observed for the devices on as-deposited film, even after subjecting to PMA for 40 min. Conduction mechanisms contributing to gate leakage current are extracted for the investigated Al₂O₃/SiC capacitors and are found to be trapfilled limit process at low-field regions; trapassisted tunneling in the mid-field regions and Fowler–Nordheim (FN) tunneling are dominating in high-field regions.

The effect of PDA and PMA on the structural and electrical characteristics of Pd/Al₂O₃/SiC capacitors suitable for flash memory applications is investigated in this paper.

A capacitor is a basic electronic passive component. Thick‐film technology allows manufacturing of capacitors covering the range of small and medium capacitances and they have been investigated in depth already. Low temperature co‐fired ceramics (LTCC) technology makes it possible to fabricate buried capacitors, which leads to increased packaging density, but such components’ properties are not well known. The purpose of this paper is to present the results of investigations on thick‐film and LTCC capacitors made in various technological variants.

Thick‐film and LTCC capacitors were made in various technological variants. Different capacitor inks, metallurgy of electrodes and component constructions were investigated. Basic electrical properties and stability were determined. An electrical equivalent circuit of such components was developed based on frequency and temperature characteristics.

Simple electrical equivalent circuits of self‐made thick‐film and LTCC micro‐capacitors were developed based on measurements in frequency and temperature domain. Good fitting accuracy was obtained. The bulk material section of model is predominant in the low‐frequency range. Interface region and serial resistance influence are revealed at higher frequency, affecting mainly dissipation factor value. Also, temperature and thermal ageing have affected strongly on that part of the model.

The paper usefully examines the electrical properties and electrical equivalent models of thick‐film and LTCC micro‐capacitors.

The objectives of this study are to assess the utility of the high‐Tc superconductor, yttrium barium copper oxide (YBCO), as a gate material in two‐ and three‐terminal superconductor‐insulator‐semiconductor (SulS) devices, and to study the electrical properties of the insulator and the insulator/Si interface. The YBCO and yttria‐stabilised‐zirconia (YSZ) layers were epitaxially grown on Si by pulsed‐laser deposition. The SulS diodes were fabricated using standard lithographic techniques, with evaporated gold providing the gate and substrate contacts. Electrical characterisation of these superconducting devices is performed using current vs. voltage and capacitance vs. voltage (C‐V) measurements under bias‐temperature cycling. It is found that deposition of thicker YBCO films (≥ 1500 A) minimises the leakage current of the devices, resulting in electrically stable capacitors, especially at superconducting temperatures. A thermally activated process in the temperature range 80–295 K, as determined from flat‐band shifts of C‐V curves, is attributed to trapping/detrapping mechanisms in the SiOx interfacial layer between YSZ and Si. The mobile ions present in YSZ, which affect the room‐temperature C‐V behaviour, give rise to adjustable threshold voltages at superconducting temperatures. These findings will have a significant impact on future transistors using this capacitor as the gate structure.

The purpose of this paper is to investigate the effect of high-k material HfO₂ as a buffer layer for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate.

RF-sputtered Pb[Zr0.35Ti0.65]O₃ or (PZT) and plasma-enhanced atomic layer deposited HfO₂ films were selected as the ferroelectric and high-k buffer layer, respectively, for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate. Multiple angle ellipsometry and X-ray diffraction analysis was carried out to obtain the crystal orientation, refractive index and absorption coefficient parameters of the deposited/annealed films. In the different range of annealing temperature, the refractive index was observed in the range of 2.9 to 2 and 1.86 to 2.64 for the PZT and HfO₂ films, respectively

Electrical and ferroelectric properties of the dielectric and ferroelectric films and their stacks were obtained by fabricating the metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal, metal/insulator/silicon and MFeIS capacitor structures. A closed hysteresis loop with remnant polarization of 4.6 µC/cm² and coercive voltage of 2.1 V was observed in the PZT film annealed at 5000 C. Introduction of HfO₂ buffer layer (10 nm) improves the memory window from 5.12 V in MFeS to 6.4 V in MFeIS structure with one order reduction in the leakage current density. The same MFeS device was found having excellent fatigue resistance property for greater than 1010 read/write cycles and data retention time more than 3 h.

The MFeIS structure has been fabricated with constant PZT thickness and varied buffer layer (HfO₂) thickness. Electrical characteristics shows the improved leakage current and memory window in the MFeIS structures as compared to the MFeS structures. Optimized MFeIS structure with 10-nm buffer layer shows the excellent ferroelectric properties with endurance greater than E10 read/write cycles and data retention time higher than 3 h. The above properties indicate the MFe(100 nm)I(10 nm)S gate stack as a potential candidate for the FeFET-based nonvolatile memory applications.

Development of (1T-type) ferroelectric random access memory (FeRAM) has most actively progressed since 1995 and motivated by the physical limits and technological drawbacks of the flash memory. 1T-type FeRAM implements ferroelectric layer at the field effect transistor (FET) gate. During the course of the investigation, it was very difficult to form a thermodynamically stable ferroelectric-semiconductor interface at the FET gate, leading to the introduction of one insulating buffer layer between the ferroelectric and the silicon substrate to overcome this problem. In this study, Al₂O₃ a high-k buffer layer deposited by plasma enhanced atomic layer deposition (PEALD) is sandwiched between the ferroelectric layer and silicon substrate.

Ferroelectric/high-k gate stack were fabricated on the silicon substrate and pt electrode. Structural characteristics of the ferroelectric (PZT) and high-k (Al₂O₃) thin film deposited by RF sputtering and PEALD, respectively, were optimized and investigated for different process parameters. Metal/PZT/Metal, Metal/PZT/Silicon, Metal/PZT/Al₂O₃/Silicon structures were fabricated and electrically characterized to obtain the memory window, leakage current, hysteresis, PUND, endurance and breakdown characteristics.

XRD pattern shows the ferroelectric perovskite thin Pb[Zr_0.35Ti_0.65]O₃ film with (101) tetragonal orientation deposited by sputtering and PEALD Al₂O₃ with (312) orientation showing amorphous nature. Multiple angle analysis shows that the refractive index of PZT varies from 2.248 to 2.569, and PEALD Al₂O₃ varies from 1.6560 to 1.6957 with post-deposition annealing temperature. Increase in memory window from 2.3 to 8.4 V for the Metal-Ferroelectric-Silicon (MFS) and Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure has been observed at the annealing temperature of 500°C. MFIS structure with 10 nm buffer layer shows excellent endurance of 3 × 109 read-write cycles and the breakdown voltage of 33 V.

This paper shows the feature, principle and improvement in the electrical properties of the fabricated gate stack for 1T-type nonvolatile FeFET. The insulating buffer layer sandwiched between ferroelectric and silicon substrate acts as a barrier to ferroelectric–silicon interdiffusion improves the leakage current, memory window, endurance and breakdown voltage. This is perhaps the first time that the combination of sputtered PZT on the PEALD Al₂O₃ layer is being reported.

The purpose of this paper is to report on metal‐oxide‐semiconductor (MOS) capacitor‐based O₂ sensors with different catalytic metal electrode (Al or Pd), deposited on both smooth and porous surface (pore diameter ranging from 2.76 to 71.6 μm) of ZrO₂ thin film.

The ZrO₂ thin film has been prepared by RF sputtering and DC magnetron sputtering process followed by thermal oxidation process, whereas the electrodes were deposited on thin film by thermal evaporation. The sensors are exposed to O₂ gas ambient at room temperature and the O₂ sensing performance has been examined by surface characterizations and on‐line sensing electrical characterizations.

MOS capacitor O₂ sensor with Pd electrode on porous ZrO₂ thin film has the best sensitivity in term of both adsorption and desorption of gas. This sensor is proved to be operated in both capacitor and diode modes.

The paper demonstrates that room temperature MOS‐based O₂ sensor operates in capacitor and diode mode conditions with focus on the effect of ZrO₂ surface morphology on the sensing properties.

This study aims to investigate the effect of temperature applied at the initial deposition of Aluminium Nitride (AlN) thin-film on a silicon substrate by high-power impulse magnetron sputtering (HiPIMS) technique.

HiPIMS system was used to deposit AlN thin film at a low output power of 200 W. The ramping temperature was introduced to substrate from room temperature to maximum 100°Cat the initial deposition of thin-film, and the result was compared to thin-film sputtered with no additional heat. For the heat assistance AlN deposition, the substrate was let to cool down to room temperature for the remaining deposition time. The thin-films were characterized by X-ray diffraction (XRD) and atomic force microscope (AFM) while the MIS Schottky diode characteristic investigated through current-voltage response by a two-point probe method.

The XRD pattern shows significant improvement of the strong peak of the c-axis (002) preferred orientation of the AlN thin-film. The peak was observed narrowed with temperature assisted where FWHM calculated at 0.35° compared to FWHM of AlN thin film deposited at room temperature at around 0.59°. The degree of crystallinity of bulk thin film was improved by 28% with temperature assisted. The AFM images show significant improvement as low surface roughness achieved at around 0.7 nm for temperature assisted sample compares to 3 nm with no heat applied.

The small amount of heat introduced to the substrate has significantly improved the growth of the c-axis AlN thin film, and this method is favorable in the deposition of the high-quality thin film at the low-temperature process.

The purpose of this study was to design, fabricate and test devices based on transformers integrated with low-temperature co-fired ceramic (LTCC) modules with isolation between primary and secondary windings at the level between 6 and 12 kV.

Insulating properties of the LTCC were examined. Dielectric strength and volume resistivity were determined for common LTCC tapes: 951 (DuPont), 41020, 41060 (ESL), A6M (Ferro) and SK47 (KEKO). According to the determined properties, three different devices were designed, fabricated and tested: a compact DC/DC converter, a galvanic separator for serial digital bus and a transformer for high-voltage generator.

Breakdown field intensity higher than 40 kV/mm was obtained for the test samples set, whereas the best breakdown field intensity of about 90 kV/mm was obtained for 951 tape. The materials 41020 and 951 exhibited the highest volume resistivity. Fabricated devices exhibited safe operation up to a potential difference of 10 kV, limited by minimum clearance. Long-term stability was assured by over 20 kV strength of inner dielectric.

This paper contains description of three devices made in the LTCC technology for application in systems with high-voltage isolation requirement, for example, for power or railway power networks.

The results show that LTCC is a suitable material for fabrication of high-voltage devices with integrated passives. Technology and properties of three examples of such devices are described, demonstrating the ability of the LTCC technology for application in reliable high-voltage devices and systems.