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1 – 10 of 398Dongkyu Shin, Igor Golosnoy and John McBride
The purpose of this paper is to investigate a reliable evaluator of arc re-ignition and to develop a numerical tool for accurate prediction of arc behaviour of low-voltage…
Abstract
Purpose
The purpose of this paper is to investigate a reliable evaluator of arc re-ignition and to develop a numerical tool for accurate prediction of arc behaviour of low-voltage switching devices (LVSDs) prior to empirical laboratory testing of real products.
Design/methodology/approach
Two types of interruption tests have been carried out in the investigation of re-ignition evaluators. Arc modelling tool coupled with the load circuit has been developed to predict arc characteristics based on conventional magnetohydrodynamics theory, with special attention given to Lorentz force acting on the arc column and surface phenomena on the splitter plate. The model assumptions have been validated by experimental observation of arc motion and current and voltage waveforms.
Findings
It is found that the exit-voltage across the switching device and the ratio of system to exit-voltage at the current zero point are reliable evaluators for prediction of re-ignition. Where the voltage ratio is positive, instantaneous re-ignition does not occur. Further, the probability of re-ignition is very low if the voltage ratio is in the rage of −1.3 to 0.
Originality/value
It is observed that the voltage ratio can be considered as a reliable global evaluator of re-ignition, which can be used for various types of LVSD test conditions. In addition, it is shown that arc modelling allows a good prediction of the current and voltage waveforms, arc motion as well as the exit-voltage, which can be used to obtain the evaluator of re-ignition.
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Trade quotas were mentioned at the 3rd ICAA, though the main topics were the state‐of‐the‐art, part and equipment design, justifying investment and types of equipment. Brian Rooks…
Abstract
Trade quotas were mentioned at the 3rd ICAA, though the main topics were the state‐of‐the‐art, part and equipment design, justifying investment and types of equipment. Brian Rooks reports from this conference where over twenty countries were represented.
Abhay Sanjay Vidhyadharan and Sanjay Vidhyadharan
Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect…
Abstract
Purpose
Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels.
Design/methodology/approach
The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented.
Findings
The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%.
Originality/value
The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.
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Yiwei Qiao, Wenrong Yang, Tianchen Huo, Guohang Chen, Haojie Zhang and Junling Luan
The purpose of this paper is to study conducted electromagnetic interference (EMI) of the high-low voltage DC/DC converter based on GaN high-electron-mobility transistors (HEMTs…
Abstract
Purpose
The purpose of this paper is to study conducted electromagnetic interference (EMI) of the high-low voltage DC/DC converter based on GaN high-electron-mobility transistors (HEMTs) in electric vehicle, and design EMI filters to suppress the conducted EMI.
Design/methodology/approach
The conducted EMI propagation model is established through simulation and analysis studying the influences of parasitic parameters, operation mode, output power and near-field capacitive coupling effects on conducted EMI of the DC/DC converter and comparing the suppression effects of EMI filters with different topologies to select the best EMI filter.
Findings
It is shown that parasitic parameters, operation mode, output power and near-field capacitive coupling effects can affect the conducted EMI of the DC/DC converter, and EMI filters of the CLC topology can effectively suppress the conducted EMI below the limit of CISPR 25.
Originality/value
Analysis of conducted EMI and design of EMI filters greatly facilitate further explorations and studies on EMI problems of the high-low voltage DC/DC converter based on GaN HEMTs.
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Hugo dos Santos Marques and Maria Beatriz Borges
This paper aims to overcome the lack of methodologies for optimizing the volume of bulky low-frequency inductors that the authors came across with when working on the design of…
Abstract
Purpose
This paper aims to overcome the lack of methodologies for optimizing the volume of bulky low-frequency inductors that the authors came across with when working on the design of hybrid active power filters. Sound work was published concerning this well-known technology, but it became evident that the mentioned optimization topic was left unaddressed.
Design/methodology/approach
Using the Lagrange multipliers optimization method combined with the electromagnetic laws of inductor design, it was possible to establish a new design method to determine the optimal solutions that fulfil any given scenario of specifications. In other words, it is now possible to obtain the inductor’s geometric and electric parameters that not only satisfy the system’s electromagnetic requirements but also lead to smaller, lighter or economical solutions.
Findings
A generalized set of equations was obtained to facilitate the calculations of all the inductor-building parameters. As expected, these equations take as inputs the inductor’s required inductance, its maximum current and the desired resistance, but also a customizable cost function. The later cost function will optimize the inductor’s volumes of copper and iron and can be settled, among other purposes, for minimizing the total weight, volume or cost.
Originality/value
All the mathematical expressions to obtain the general optimal solutions are given as well as practical graphics for the three above-mentioned optimization criteria. Using these charts, the reader will be able to obtain by simple inspection the optimal solutions for a large, generalized universe of intended specifications.
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Sumathy P., Navamani Divya, Jagabar Sathik, Lavanya A., Vijayakumar K. and Dhafer Almakhles
This paper aims to review comprehensively the different voltage-boosting techniques and classifies according to their voltage gain, stress on the semiconductor devices, count of…
Abstract
Purpose
This paper aims to review comprehensively the different voltage-boosting techniques and classifies according to their voltage gain, stress on the semiconductor devices, count of the total components and their prominent features. Hence, the focus is on non-isolated step-up converters. The converters categorized are analyzed according to their category with graphical representation.
Design/methodology/approach
Many converters have been reported in recent years in the literature to meet our power requirements from mill watts to megawatts. Fast growth in the generation of renewable energy in the past few years has promoted the selection of suitable converters that directly impact the behaviour of renewable energy systems. Step-up converters are a fast-emerging switching power converter in various power supply units. Researchers are more attracted to the derivation of novel topology with a high voltage gain, low voltage and current stress, high efficiency, low cost, etc.
Findings
A comparative study is done on critical metrics such as voltage gain, switch voltage stress and component count. Besides, the converters are also summarized based on their advantages and disadvantages. Furthermore, the areas that need to be explored in this field are identified and presented.
Originality/value
Types of analysis usually performed in dc converter and their needs with the areas need to be focused are not yet completely reviewed in most of the articles. This paper gives an eyesight on these topics. This paper will guide the researchers to derive and suggest a suitable topology for the chosen application. Moreover, it can be used as a handbook for studying the various topologies with their shortfalls, which will provide a way for researchers to focus.
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Vaithiyanathan D., Megha Singh Kurmi, Alok Kumar Mishra and Britto Pari J.
In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more…
Abstract
Purpose
In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications.
Design/methodology/approach
The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit.
Findings
The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased.
Originality/value
The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.
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Harikrishnan Ramiah and Tun Zainal Azni Zulkifli
This paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a WLAN…
Abstract
Purpose
This paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a WLAN transmitter application in 0.18‐μm deep submicron CMOS technology.
Design/methodology/approach
A folded current draining low‐voltage mixer architecture is explored and an extensive simulation carried out utilizing Cadence Spectre‐RF tool in optimizing the linearity, input third‐order intercept point (IIP3), the dynamic range, 1 dB compression point (P−1dB), power dissipation and reduction of switching quad Cgs, input gate‐source capacitance, in enhancing the switching efficiency of the proposed architecture.
Findings
A highly linear, high input dynamic range, low voltage folded up‐conversion mixer architecture is realized in a significant comparable performance with respect to conventional reported architecture, indicating −8.87 dBm of OIP3 corresponding to 15.27 dBm IIP3 and 4.37 dBm of P−1dB in 0.18‐μm CMOS technology.
Research limitations/implications
The optimized mixer architecture is stringent to an up‐converter application. To be utilized as a down converter at the receiver end, parameters, namely as noise figure and conversion gain, are of additional importance.
Practical implications
The designed folded mixer architecture is in need of integration to a two‐step up‐conversion transmitter architecture which relaxes the injection pulling effect for a given low voltage headroom, with low power dissipation design.
Originality/value
In this work, an integrated folded architecture with on‐chip process, voltage and temperature compensated biasing circuit is explored and enhanced, raising awareness of adapting improved multiplier blocks in achieving optimal performance in WLAN transceiver architecture.
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This work aims to improve upon the linearity of integrated CMOS current sensors used in switch mode power supply topologies, using a low-cost and low-voltage (less than 1.2 V…
Abstract
Purpose
This work aims to improve upon the linearity of integrated CMOS current sensors used in switch mode power supply topologies, using a low-cost and low-voltage (less than 1.2 V) CMOS technology node. Improved sensor accuracy contributes to efficiency in switched supplies by reducing measurement errors when it is integrated with closed-loop control.
Design/methodology/approach
Integrated current-sensing methods were investigated and CMOS solutions were prioritized. These solutions were implemented and characterized in the desired process and shortcomings were identified. A theoretical analysis accompanied by simulated tests was used to refine improvements which were prototyped. The current sensor prototypes were fabricated and tested.
Findings
Measured and simulated results are presented which show improved linearity in current sensor outputs. Techniques borrowed from analog amplifier design can be used to improve the dynamic range and linearity of current-steered CMOS pairs for measuring current. A current sensor with a gain of 5 V/A operating in a 10 MHz switch mode supply environment is demonstrated.
Originality/value
This paper proposes an alternative approach to creating suitable bias conditions for linearity in a SenseFET topology. The proposed method is compact and architecturally simple in comparison to other techniques.
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Mazdak Ebadi, Negin Abbasi and Hamidreza Maghsoudi
This paper aims to propose an integrated protection scheme for converters of a low-power, low-cost photovoltaic system. Power electronic converters use a variety of methods to…
Abstract
Purpose
This paper aims to propose an integrated protection scheme for converters of a low-power, low-cost photovoltaic system. Power electronic converters use a variety of methods to limit overload and fault current. The use of insulated and non-insulated sensors along with additional circuits to detect and limit fault current can cause current to be limited or completely cut off before damage to semiconductor devices. In addition, fuses that have slower performance are used as backup for any type of protection.
Design/methodology/approach
First, all the candidate points for protection are investigated. In this paper, after examining the performance of glass fuses as linear resistors, they are used as a current feedback element. A simple, isolated and reliable circuit for fault detection at various points of the system has been proposed that can be implemented and operated in single shot or auto-reclose operating mode.
Findings
The experimental results of this circuit on a dc/dc converter and an H-bridge inverter show that it can cut off all instantaneous short circuit errors in less than 50 µs and prevent damage to the semiconductor switch.
Originality/value
In low-cost and low-power converters, it is usually not cost-effective to use complex and expensive devices. For this reason, these converters are more vulnerable to faults. On the other hand, in complex systems such as photovoltaics, several converters are used simultaneously in different parts, and the occurrence of a fault in each of them causes the whole system to fail.
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