Search results

The purpose of this paper is to present a selective wet‐etching method of boron doped low‐pressure chemical vapour deposition (LPCVD) polysilicon film for the realization of piezoresistors over the bulk micromachined diaphragm of (100) silicon with improved yield and uniformity.

The method introduces discretization of the LPCVD polysilicon film using prior etching for the grid thus dividing each chip on the entire wafer. The selective etching of polysilicon for realizing of piezoresistors is limited to each chip area with individual boundaries.

The method provides a uniform etching on the entire silicon wafer irrespective of its size and leads to economize the fabrication process in a batch production environment with improved yield.

The method introduces one extra process step of photolithography and subsequent etching for discretizing the polysilicon film.

The method is useful to enhance yield while defining metal lines for contact purposes on fabricated electronic structures using microelectronics. Stress developed in LPCVD polysilicon can be removed using proposed approach of discretization of polysilicon film.

The work is an outcome of regular fabrication work using conventional approaches in an R&D environment. The proposed method replaces the costly reactive ion etching techniques with stable reproducibility and ease in its implementation.

This paper aims to clarify adequate control characteristics for using a control chart on the basis of a case study of the low‐pressure chemical vapor deposition (LPCVD) process, which is one of the semiconductor manufacturing processes.

The paper opted for a simulation study using the data generated by EWMA model and the real data obtained from the LPCVD process.

The paper provides adequate control characteristics for control charts. It suggests that it is desirable to employ both the quality characteristic and the process rate for monitoring when the process was modeled by the EWMA model. Furthermore, if only one control characteristic is employed, then the process rate is the most adequate characteristic.

This paper newly proposes the process rate as a control characteristic for control charts.

A MEMS process is described to control diaphragm thickness with an integrated provision for back to front alignment in the fabrication of a polysilicon piezoresistive pressure sensor. The end point detection for the diaphragm etching is suitably incorporated in the process so that it is also used for the back‐to‐front alignment. The proposed process is cost‐effective and suitable for the batch fabrication of the pressure sensor.

To fabricate submicrometer thin membrane of silicon nitride and silicon dioxide over an anisotropically etched cavity in (100) silicon.

PECVD of silicon dioxide and Silcion nitride layers of compatible thicknesses followed by thermal annealing in nitrogen ambients at 1,000°C for 30 min, leads to stable membrane formation. Anisotropic etching of (100) silicon below the membrane through channels on the sides has been used with controlled cavity dimensions.

Lateral front side etching through channels slows down etching rate drastically. The etching mechanism has been discussed with experimental details.

Vacuum sealed cavity membranes can be realised for micro sensor applications.

The process is new and feasible for micro sensor technologies.

The purpose of this paper is to describe the fabrication of a miniaturized membrane type double cavity vacuum‐sealed micro sensor for absolute pressure using front‐side lateral etching technology.

Potassium hydroxide‐based anisotropic etching of single crystal silicon is used to realize the cavities under the membrane type diaphragms through channels on the sides. The diaphragms consist of composite layers of plasma‐enhanced chemical vapour deposition (PECVD) of silicon nitride and silicon dioxide. PECVD of silicon dioxide is done for sealing the channels and the cavity in vacuum. Boron thermal diffusion in low‐pressure chemical vapour deposition of polysilicon layer over the membrane is done for realizing resistors. The fabricated device uses Wheatstone half bridge circuit to read the variation of resistance with respect to an applied pressure.

A double cavity vacuum‐sealed absolute pressure micro sensor has been fabricated successfully using front‐side lateral etching technology and has been measured for pressure range of 0‐0.45 MPa. The measured pressure sensitivity of two pressure sensors is 9.28 and 10.44 mV/MPa.

The paper shows that front‐side lateral etching technology is feasible in the fabrication of small vacuum‐sealed cavities and absolute pressure sensors.

The purpose of this paper is to use finite element method for optimizing the membrane type double cavity vacuum sealed structure for the best achievable sensitivity in a piezoresistive absolute pressure sensor and its validation using a standard complementary metal oxide semiconductor (CMOS) process.

A double cavity vacuum sealed piezoresistive absolute pressure sensor has been simulated and optimized for its performance and an analytical model describing the behaviour of the sensor has been described. The 1×1 mm sensor chip has two membrane type 100×30×1.7 μm diaphragms consisting of composite layers of plasma enhanced chemical vapour deposition (PECVD) of silicon nitride (Si₃N₄) and silicon dioxide (SiO₂) each hanging over 21 μm deep rectangular cavity. Potassium hydroxide (KOH) based anisotropic etching of single crystal silicon using front side lateral etching technology is used for the fabrication of the sensor. The electrical readout circuitry uses 318 Ω boron diffused low pressure vapour chemical vapour deposition (LPCVD) of polysilicon resistors arranged in the Wheatstone half bridge configuration. The sensing structure is simulated and optimized using COMSOL Multiphysics.

Front-side lateral etching technology has been successfully used for the fabrication of double cavity absolute pressure sensor. A good agreement with the fabricated device for the chosen location of the piezoresistors through simulation has been predicted. The measured pressure sensitivity of two tested pressure sensors is 12.63 and 12.46 mV/MPa, and simulated pressure sensitivity is found to be 12.9 mV/MPa for pressure range of 0 to 0.5 MPa. The location of the piezoresistor has also been optimized using the simulation tools for enhancing the sensor sensitivity to 62.14 mV/MPa. The pressure sensitivity is further enhanced to 92 mV/MPa by increasing the width of the diaphragm to 35 μm.

The simulated and measured pressure sensitivities of the double cavity pressure sensor are in close agreement. Sevenfold enhancement in the pressure sensitivity of the optimized sensing structure has been observed. The proposed front-side lateral etching technology can be adopted for making membrane type diaphragms hanging over vacuum sealed micro-cavities for high sensitivity pressure sensing applications.

Describes the key attributes of MEMS technology and existing and future business opportunities. Discusses the various stages in the fabrication of MEMS devices and offers guidance regarding the selection of processing methods for deposition, lithography and etching. Also describes the MEMS‐Exchange program and associated network of fabrication centres.

A single wafer silicon condenser microphone with a novel single deeply corrugated diaphragm is presented in this paper. The microphone diaphragm with corrugation depth of 100 μm is only 1 mm² in area, while the open‐circuit sensitivity as high as 9.8 mV/Pa under a bias voltage of 6 V has been obtained. The recorded frequency bandwidth is about 20 kHz. The measurements show reasonable agreements with the theoretical predictions.

Thermopile infrared (IR) detectors are one of the most important IR devices. Considering that the surface area of conventional four-end-beam (FEB)-based thermopile devices cannot be effectively used and the performance of this type of devices is relatively low, this paper aims to present a double-end-beam (DEB)-based thermopile device with high duty cycle and performance. The paper aims to discuss these issues.

Numerical analysis was conducted to show the advantages of the DEB-based thermopile devices.

Structural size of the DEB-based thermopiles may be further scaled down and maintain relatively higher responsivity and detectivity when compared with the FEB-based thermopiles. The authors characterized the thermoelectric properties of the device proposed in this paper, which achieves a responsivity of 1,151.14 V/W, a detectivity of 4.15 × 108 cm Hz1/2/W and a response time of 14.46 ms sensor based on DEB structure.

The paper proposed a micro electro mechanical systems (MEMS) thermopile infrared sensor based on double-end-beam structure.

The purpose of this study is to present reports on fabrication of silicon (Si) nanowires (NWs). The study consists of microwire formation on silicon-on-insulator (SOI) that was fabricated using a top-down approach which involved conventional photolithography coupled with shallow anisotropic etching.

A 5-inch p-type silicon-on-insulator (SOI) coated with 250nm layer and Photoresist (PR) with thickness of 400nm is coated in order to make pattern transfer via binary mask, after the exposure and development, a resist pattern between 3 μm-5 μm were obtained, Oxygen plasma spreen was used to reduce the size of the PR to 800 μm, after this, the wafer with 800 μm was loaded into SAMCO inductively coupled plasma (ICP)-RIE and got silicoon microwire was obtained. Next, the sample was put into an oxidation furnace for 15, 30, 45 and 60 minutes and the sample was removed and dipped into a buffered oxide etch solution for five minutes to remove all the SiO₂ ashes.

The morphological characterization was conducted using scanning electron microscopy and atomic force microscopy. At terminal two, gold electrodes which were designated as source and drain were fabricated on top of individual NWs using conventional lithography electrical and chemical response. Once the trimming process has been completed, the device's current–voltage (I-V) characteristic was measured by using a Keithley 4200 semiconductor parameter analyser. Devices with different width of wires approximately 20, 40, 60 and 80 nm were characterized. The wire current variation as a function of the pH variation in voltage was investigated: pH monitoring for variations of pH values between 5 and 9.

This paper provides useful information on novel and yet simple cost-effective fabrication of SiNW; as such, it should be of interest to a broad readership, especially those interested in micro/nanofabrication.