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Article
Publication date: 21 June 2013

Yong‐Won Lee, Keun‐Soo Kim and Katsuaki Suganuma

The purpose of this paper is to study the effect of the electropolishing time of stencil manufacturing parameters and solder‐mask definition methods of PCB pad design parameters…

Abstract

Purpose

The purpose of this paper is to study the effect of the electropolishing time of stencil manufacturing parameters and solder‐mask definition methods of PCB pad design parameters on the performance of solder paste stencil printing process for the assembly of 01005 chip components.

Design/methodology/approach

During the study, two types of stencils were manufactured for the evaluations: electroformed stencils and electropolished laser‐cut stencils. The electroformed stencils were manufactured using the standard electroforming process and their use in the paste printing process was compared against the use of an electropolished laser‐cut stencil. The electropolishing performance of the laser‐cut stencil was evaluated twice at the following intervals: 100 s and 200 s. The performance of the laser‐cut stencil was also evaluated without electropolishing. An optimized process was established after the polished stencil apertures of the laser‐cut stencil were inspected. The performance evaluations were made by visually inspecting the quality of the post‐surface finishing for the aperture wall and the quality of that post‐surface finishing was further checked using a scanning electron microscope. A test board was used in a series of designed experiments to evaluate the solder paste printing process.

Findings

The results demonstrated that the length of the electropolishing time had a significant effect on the small stencil's aperture quality and the solder paste's stencil printing performance. In this study, the most effective electropolishing time was 100 s for a stencil thickness of 0.08 mm. The deposited solder paste thickness was significantly better for the enhanced laser‐cut stencil with electropolishing compared to the conventional electroformed stencils. In this printing‐focused work, print paste thickness measurements were also found to vary across different solder‐mask definition methods of printed circuit board pad designs with no change in the size of the stencil aperture. The highest paste value transfer consistently occurred with solder‐mask‐defined pads, when an electropolished laser‐cut stencil was used.

Originality/value

Due to important improvements in the quality of the electropolished laser‐cut stencil, and based on the results of this experiment, the electropolished laser‐cut stencil is strongly recommended for the solder paste printing of fine‐pitch and miniature components, especially in comparison to the typical laser‐cut stencil. The advantages of implementing a 01005 chip component mass production assembly process include excellent solder paste release, increased solder volume, good manufacture‐ability, fast turnaround time, and greater cost saving opportunities.

Details

Soldering & Surface Mount Technology, vol. 25 no. 3
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 29 April 2014

Seok-Hwan Huh, Kang-Dong Kim and Keun-Soo Kim

The purpose of this paper is to evaluate the relationship between the Cu trace and epoxy resin and to check the validity of surface and interfacial cutting analysis system…

Abstract

Purpose

The purpose of this paper is to evaluate the relationship between the Cu trace and epoxy resin and to check the validity of surface and interfacial cutting analysis system (SAICAS) by comparing its results to those of the 90° peel test.

Design/methodology/approach

In this study, the effects of surface morphology on the adhesion strength were studied for a Cu/epoxy resin system using a SAICAS. In order to evaluate the peel strength of the sample, the curing degree and surface morphology of the epoxy resin were varied in the Cu/epoxy resin system.

Findings

The results indicated that the peel strength is strongly affected by the curing degree and the surface morphology of the epoxy layer. As the pre-cure time increased, the interactions between the epoxy resin and permanganate during the adhesion promotion process decreased, which decreased the surface roughness (Ra) of the resin. Therefore, the surface roughness of the epoxy resin decreased with increasing pre-cure time. The curing degree was calculated with the FTIR absorption peak (910 cm−1) of the epoxy groups. The high curing degree for the epoxy resin results in a coral-like morphology that provides a better anchoring effect for the Cu trace and a higher interfacial strength.

Research limitations/implications

It is necessary to study the further adhesion strength, i.e. the friction energy, the plastic deformation energy, and the interfacial fracture energy, in micro- and nanoscale areas using SAICAS owing to insufficient data regarding the effects of size and electroplating materials.

Originality/value

From findings, it is found that measuring the peel strength using SAICAS is particularly useful because it makes the assessment of the peel strength in the Cu/epoxy resin system of electronic packages possible.

Details

Circuit World, vol. 40 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 2 November 2015

Seok-Hwan Huh, Sung-Ho Choi, An-Seob Shin, Gi-Ho Jeong, Suk-Jin Ham and Keun-Soo Kim

This study aims to elucidate the reaction mechanism of electroless NiP deposits on conductive but non-catalytic Cu films on the basis of their nucleation and growth without Pd…

Abstract

Purpose

This study aims to elucidate the reaction mechanism of electroless NiP deposits on conductive but non-catalytic Cu films on the basis of their nucleation and growth without Pd catalyst and to measure the deposition rate and activation energy of electroless NiP deposits on the non-catalytic Cu film at various deposition times (60, 120, 240 and 480 s) and temperatures (70, 80 and 90°C) at pH 4.6.

Design/methodology/approach

Specimens with and without Pd catalyst on Cu film were prepared as follows: the Pd catalyst was deposited on half of the Cu film using a deposition protector, and the specimen containing the Pd catalyst deposited on half of its area was immersed in electroless NiP solution. The growth of NiP on the Cu films with and without the Pd catalyst was observed.

Findings

The number of Pd nanoparticles increased with Pd activation time; the nucleation of Pd dominated over growth at 60 s. Lattice images show that the d-spacing of Ni nanoparticles doped with less than 10 at% P increased to 2.050 Å. Nucleation of NiP deposits occurred simultaneously in the specimens with and without the Pd catalyst, because electrons could be transferred via the conductive Cu. Therefore, the reaction mechanism of the electroless NiP deposited on Cu film appears to be electrochemical. The activation energies for NiP deposits (15 s Pd with catalytic Pd, 15 s Pd without catalytic Pd, 60 s Pd with catalytic Pd and 60 s Pd without catalytic Pd) on the Cu film are 65.8, 64.0, 64.3 and 58.1 kJ/mol, respectively. This demonstrates that, regardless of the volume and the presence of catalytic Pd, the activation energy of electroless NiP has a consistent value.

Research limitations/implications

It is necessary to study the relationship between the volume of Pd nanoparticles and the nucleation rate of NiP at an initial stage, as there are limited data regarding the effect of Pd volume on the nucleation rate of NiP.

Originality/value

The reaction mechanism of the electroless NiP deposited on conductive but non-catalytic Cu film involves electrochemical reactions because the nucleation of NiP deposits occurs on conductive Cu film regardless of the presence of the Pd catalyst.

Details

Circuit World, vol. 41 no. 4
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 20 September 2011

Yong‐Won Lee, Keun‐Soo Kim and Katsuaki Suganuma

The purpose of this paper is to optimize assembly processes in order to minimize defects in the assembly of 01005 chip components.

Abstract

Purpose

The purpose of this paper is to optimize assembly processes in order to minimize defects in the assembly of 01005 chip components.

Design/methodology/approach

During the study, solder paste printing process‐related variables, such as solder paste type, stencil type, and stencil opening ratio, and pick and place process‐related methods, such as vision camera type and vacuum pickup nozzle type were evaluated with the goal of achieving a high‐yield assembly solution for 01005 chip components. A test board was used in a series of designed experiments to optimize the solder paste printing, pick and placement, and reflow processes. Assembly defects were analyzed as a function of the stencil design and the assembly processes.

Findings

The results of the study indicated that both electroformed and electropolished laser‐cut stencils had a comparable print quality with respect to the solder volume delivered to the pads. In terms of assembly yield performance, type 4 (size range: 20‐38 μm) solder paste with a smaller sphere size gave a better overall yield and better paste deposition on the pad, if used on a 0.08‐mm thick electroformed stencil with a 90 per cent aperture. Temperature cycling between −65 and 150°C, with up to 1,500 cycles, showed that no cracks were observed at the solder joints due to temperature cycling. The process and design change required for achieving a robust manufacturing process have been indicated and reported.

Originality/value

The results of this work provide process recommendations for the implementation of 01005‐sized chip components assembly in mass production processes.

Details

Soldering & Surface Mount Technology, vol. 23 no. 4
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 22 June 2012

Yong‐Won Lee, Keun‐Soo Kim and Katsuaki Suganuma

To propose a solution procedure to minimize/eliminate tombstoning defects in small chip components with different micro via‐in pad designs for high density module assembly.

Abstract

Purpose

To propose a solution procedure to minimize/eliminate tombstoning defects in small chip components with different micro via‐in pad designs for high density module assembly.

Design/methodology/approach

Four different micro via‐in pad designs were compared (via‐hole diameter): ultra small via‐in pads (10 μm), small via‐in pads (20 μm) and large via‐in pads (60 μm), as well as designs with no via‐in pads and capped via‐in pads. Two process variables were also evaluated for the goal of achieving a high‐yield assembly solution in micro via‐in pad and lead‐free solder conditions. Potential factors such as the preheat conditions of the reflow profile and stencil aperture size, which might affect tombstoning in components with micro via‐in pads, were investigated.

Findings

The results indicated that the micro via‐in pad design significantly increased the tombstoning; thus, tombstoning did not occur in components with both no via‐in pads and capped via‐in pads. Capped via‐in pads exhibited the best results in preventing tombstoning and provided a wide process window for the selection of process parameters. The results showed that tombstoning was found to decrease with both increasing stencil opening ratio and use of reflow profile with long‐preheat condition.

Originality/value

The paper's findings provide certain process guidelines for high density module assemblies with via‐in pad design. The strategy is to prevent tombstoning by adopting capped via‐in pad design if possible when employing micro via‐in pad technology.

Details

Soldering & Surface Mount Technology, vol. 24 no. 3
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 1 February 2013

Yong‐Won Lee, Keun‐Soo Kim and Katsuaki Suganuma

The purpose of this paper is to propose a solution procedure to minimize/eliminate voiding and spattering defects in the assembly of 0201 chip components with micro via‐in pads…

Abstract

Purpose

The purpose of this paper is to propose a solution procedure to minimize/eliminate voiding and spattering defects in the assembly of 0201 chip components with micro via‐in pads and 95 wt.%Sn‐5 wt.%Sb solder alloy.

Design/methodology/approach

In total, four different micro via‐in pad designs were compared (via‐hole opening size): ultra small via‐in pads (d: 10 μm), small via‐in pads (d: 20 μm), and large via‐in pads (d: 60 μm), as well as designs with no via‐in pads and capped via‐in pads. Two process variables were also evaluated for the goal of achieving a high‐yield assembly solution in micro via‐in pad and lead‐free solder systems. Potential factors, such as the preheat conditions of the reflow profile and stencil aperture size, which might affect voiding and spattering in solder joints with micro via‐in pad, were investigated. Solder voiding frequency and size were also determined from X‐ray inspection and sample cross‐section analysis.

Findings

The results indicated that larger via‐holes were seen to create bigger voiding than smaller via‐holes. For smaller via‐holes, spattering is a greater problem than voiding in solder joints. Ultra small via‐in pads generated higher spattering compared to no via‐in pads and capped via‐in pads. Capped via‐in pads exhibited the best results in preventing voiding and flux spattering, and provided a wide process window for the selection of process parameters. It is also indicated that spattering was found to rapidly reduced with both increasing stencil opening size and use of reflow profile with long‐preheat conditions.

Originality/value

The findings provide certain process guidelines for surface‐mount assembly with via‐in pad substrate design. The strategy is to prevent voiding and spattering by adopting capped via‐in pads, if possible, when applying micro via with the 95 wt.%Sn‐5 wt.%Sb solder alloy system.

Details

Soldering & Surface Mount Technology, vol. 25 no. 1
Type: Research Article
ISSN: 0954-0911

Keywords

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