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Article
Publication date: 15 July 2022

Khairul Mohd Arshad, Muhamad Mat Noor, Asrulnizam Abd Manaf, Kawarada H., Falina S. and Syamsul M.

Vertical-cavity surface-emitting laser (VCSEL) is a high-performance semiconductor device made of unique epitaxial layers grown on n-type GaAs or InP substrates. The…

Abstract

Purpose

Vertical-cavity surface-emitting laser (VCSEL) is a high-performance semiconductor device made of unique epitaxial layers grown on n-type GaAs or InP substrates. The VCSEL’s thermal resistance, Rth, is an essential metric that reflects its thermal properties and dependability. The purpose of this paper is to develop packaging for 1 mm2 VCSEL chips made of a variety of materials, such as ceramic, lead frame and printed circuit board (PCB)-based packaging, as well as provide an idea or design that can withstand and perform well in terms of Rth and heat dissipation during operation. SolidWorks 2017 and AutoCAD Mechanical 2017 software were used to publish all thoughts and ideas, including the size dimensions (x, y and z) and material choices for each package.

Design/methodology/approach

Following the modelling and material selection, the next step is to use the Ansys Mechanical Structural FEA Analysis software to simulate all packaging for Rth and determine which packaging produced the best result, therefore, determining the heat dissipation for each packing. All parameters were used based on the standard cleanroom requirement for the industrial manufacturing backend process, where the cleanroom classification is 10,000 particles (ISO 7). The results demonstrated that the ceramic and lead frame provided good Rth values of 7.3 and 7.0 K/W, respectively, when compared to the PCB, which provided more than 80 K/W; thus, the heat dissipation for PCB packaging also increased.

Findings

As a result of the research, it was determined that ceramic and lead frame packaging are appropriate and capable of delivering good Rth and heat dissipation values when compared to PCB. In comparison to PCB, which requires numerous modifications, such as adding via holes and a thermal bar in an attempt to lower the Rth value, neither packaging requires improvement. Ceramic was chosen for development based on Rth's highest performance, with the actual device consisting of a lead frame and PCB. The Zth measurement test was carried out on a ceramic package, and the Rth result was comparable to the simulation result of 7.6 K/W, indicating that simulation was already proved for research and development.

Originality/value

The purpose of this study is to determine which proposed packaging design would give the highest Rth performance of a 1 mm2 chip as well as the best heat dissipation. In comparison to other studies, VCSEL packaging used the header and window cap as package components with a wavelength of 850 nm, and other VCSEL packaging developments used the sub mount on ceramic package with an output power ranging from 500 mW to 2 W, whereas this study used a huge wavelength and an output power of 4 W.

Details

Microelectronics International, vol. 40 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 21 May 2019

Nurul Aida Farhana Othman, Sharidya Rahman, Sharifah Fatmadiana Wan Muhamad Hatta, Norhayati Soin, Brahim Benbakhti and Steven Duffy

To design and optimize the traditional aluminum gallium nitride/gallium nitride high electron mobility transistor (HEMT) device in achieving improved performance and…

Abstract

Purpose

To design and optimize the traditional aluminum gallium nitride/gallium nitride high electron mobility transistor (HEMT) device in achieving improved performance and current handling capability using the Synopsys’ Sentaurus TCAD tool.

Design/methodology/approach

Varying material and physical considerations, specifically investigating the effects of graded barriers, spacer interlayer, material selection for the channel, as well as study of the effects in the physical dimensions of the HEMT, have been extensively carried out.

Findings

Critical figure-of-merits, specifically the DC characteristics, 2DEG concentrations and mobility of the heterostructure device, have been evaluated. Significant observations include enhancement of maximum current density by 63 per cent, whereas the electron concentration was found to propagate by 1,020 cm−3 in the channel.

Practical implications

This work aims to provide tactical optimization to traditional heterostructure field effect transistors, rendering its application as power amplifiers, Monolithic Microwave Integrated Circuit (MMICs) and Radar, which requires low noise performance and very high radio frequency design operations.

Originality/value

Analysis in covering the breadth and complexity of heterostructure devices has been carefully executed through extensive TCAD modeling, and the end structure obtained has been optimized to provide best performance.

Details

Microelectronics International, vol. 36 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 1 June 2003

B.W. Clark and D.C. Anderson

The penalty boundary method (PBM) is a new method for performing finite element analysis using a regular overlapping mesh that does not have to coincide with the geometric…

1057

Abstract

The penalty boundary method (PBM) is a new method for performing finite element analysis using a regular overlapping mesh that does not have to coincide with the geometric boundaries. The PBM uses CAD solid geometry directly to generate element matrix equations and apply boundary conditions, removing the need for a separate representation of the geometry. The preliminary results show that the PBM can significantly reduce the time and manual intervention required to prepare finite element models and perform analyses. This paper presents the PBM approach for representing the problem domain on an overlapping mesh that results in a more traditional method for applying natural boundary conditions.

Details

Engineering Computations, vol. 20 no. 4
Type: Research Article
ISSN: 0264-4401

Keywords

Article
Publication date: 1 April 2000

W.J. Plumbridge

Impressions gained from two visits to Japan, discussing with representatives of industry and academe the current status regarding the implementation of lead‐free…

247

Abstract

Impressions gained from two visits to Japan, discussing with representatives of industry and academe the current status regarding the implementation of lead‐free technology, are presented. Driven by the commercial rewards of lead‐free goods, Japan appears to have more clearly articulated targets for the removal of lead, in advance of the expected timescales in EU legislation. Various strategies for combating problems associated with the higher melting point of lead‐free solder alloys have been investigated. Design and development generally involve a broader approach than in Europe, involving stress analysis, materials properties and life prediction to underpin empirical data obtained by thermal cycling of boards. Despite the existence of several committees to facilitate the introduction of lead‐free solders, a lack of cohesion is sometimes apparent, particularly regarding heat treatment of materials prior to testing. It is proposed that a challenge as demanding as this would benefit from greater collaboration internationally.

Details

Soldering & Surface Mount Technology, vol. 12 no. 1
Type: Research Article
ISSN: 0954-0911

Keywords

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