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Article
Publication date: 1 December 2004

Teck Joo Goh, K.N. Seetharamu, G.A. Quadir, Z.A. Zainal and K. Jeevan Ganeshamoorthy

This paper presents the thermal analyses carried out to predict the temperature distribution of the silicon chip with non‐uniform power dissipation patterns and to…

Abstract

This paper presents the thermal analyses carried out to predict the temperature distribution of the silicon chip with non‐uniform power dissipation patterns and to determine the optimal locations of power generating sources in silicon chip design layout that leads to the desired junction temperature, Tj. Key thermal parameters investigated are the heat source placement distance, level of heat dissipation, and magnitude of convection heat transfer coefficient. Finite element method (FEM) is used to investigate the effect of the key parameters. From the FEM results, a multiple linear regression model employing the least‐square method is developed that relates all three parameters into a single correlation which would predict the maximum junction temperature, Tj,max.

Details

Microelectronics International, vol. 21 no. 3
Type: Research Article
ISSN: 1356-5362

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