Search results

1 – 3 of 3
Article
Publication date: 1 February 1986

J.J. Tomaine

The arrival of Large Scale Integration (LSI) devices forced the development of products which could reliably package these high density chip carriers. Until LSI, printed circuit…

Abstract

The arrival of Large Scale Integration (LSI) devices forced the development of products which could reliably package these high density chip carriers. Until LSI, printed circuit technology designers were only moderately challenged to make high density products. This change occurred in the early 1970s at IBM with the printed circuit packaging for the IBM 4300 models. This was the first system application of LSI chip carriers. Since then, numerous LSI printed circuit carrier designs have been used in IBM systems. The methods to predict reliability of the LSI printed circuit carriers have not kept up with the hardware technology. This paper will describe an enhanced method of prediction which more closely represents the performance of today's LSI printed circuit cards and mother boards. Computer processed algorithms will be used to estimate the failure rates of a particular printed circuit carrier and the effects of this estimate on the complete system will be discussed. The estimation algorithms are contained in programmes resident on floppy diskettes and run on an IBM Personal Computer. The flexibility and ease of use of the PC allows the user to make any necessary additions or changes to the algorithms quickly. The algorithms are derived from standard Weibull reliability techniques but include internally derived factors which enhance the accuracy of the Weibull predictions. Data from extensive field reporting of any defects and detailed failure analysis are used to enhance the accuracy of the algorithms. Using the enhanced algorithms, one can generate new estimates easily. Quick access and fast turnaround times result in a convenient and cost effective technique to provide these estimates to system users on a timely basis. Design changes to the carrier which could affect the reliability are quickly modelled in the algorithms and new reliability estimates are provided allowing the final user to make the required system trade‐offs easily. These design changes and new reliability projections can be presented to management in a timely manner and allow them to make the cost/performance decisions which result in the optimum marketable product.

Details

Circuit World, vol. 12 no. 3
Type: Research Article
ISSN: 0305-6120

Article
Publication date: 1 March 1989

F.W. Haining, R.F. Shaul, R.W. Keim and R.M. Murcko

The circuit elements of every printed circuit board have the potential for failure during test and/or use. These failures can occur by forming short‐circuits between adjacent…

Abstract

The circuit elements of every printed circuit board have the potential for failure during test and/or use. These failures can occur by forming short‐circuits between adjacent circuit elements, or by forming open‐circuits in the conductors. The risk sites can be identified by type, and the total number enumerated by manual inspection of the photolithographic masks used to fabricate the printed circuit layers. However, the circuit density of high performance printed circuit boards has become so great that meaningful manual analysis has become impractical. A more effective method is to use special graphics programs to analyse the computer‐aided design (CAD) data. The methodology developed to perform the CAD analysis of high performance printed circuit boards for short‐circuits utilises two powerful computer graphic tools: the Interactive Graphics System and the Unified Shapes Checking system. Test data for open‐circuits are generated using specially written alphanumeric routines. The data can be used for stress testing the printed circuit boards by wiring up special test modules that are plugged into the boards and then placing the boards into environmental test chambers. The printed circuits are checked for short‐circuits by putting them into groups that have no risk of shorting to each other (zero risk), and placing the groups in parallel under an electrical potential. The flow of current between the groups would indicate a short‐circuit. Similarly, the printed circuits can be checked for open‐circuits, by stringing them together into groups in series, and measuring the changes in resistance under thermal stress. Both types of test data can also be used for in‐process testing.

Details

Circuit World, vol. 15 no. 4
Type: Research Article
ISSN: 0305-6120

Article
Publication date: 1 September 1913

My Lord, in this case, if you brush away—as I invite you to brush away—all the irrelevancies introduced by my friend, Mr. Hume‐Williams, I submit to you with confidence that this…

Abstract

My Lord, in this case, if you brush away—as I invite you to brush away—all the irrelevancies introduced by my friend, Mr. Hume‐Williams, I submit to you with confidence that this case is reasonably clear; but the elaborate argument he has delivered requires me, I am afraid, to repeat what I said in opening, that the only way to approach a case of this kind is to look at the Section of the Statute, and to see what the Section of the Statute was intended to prohibit. I am not going to trouble you with the earlier cases decided under the Food and Drugs Act. I know there have been decisions by the Divisional Court, but they cannot be looked to because the Act under which these proceedings were taken was avowedly intended to meet the difficulties that had arisen in the administration of the earlier Acts. The purpose of the Act is absolutely clear, especially in regard to Section 3, but let me remind you again that this Act contains several different offences, provided with appropriate defences, and guarded by certain specific conditions.

Details

British Food Journal, vol. 15 no. 9
Type: Research Article
ISSN: 0007-070X

1 – 3 of 3