Search results

The purpose of this paper is to fabricate a new Cu-Sn-Ni-Cu interconnection microstructure for electromigration studies in 3D integration.

The Cu-Sn-Ni-Cu interconnection microstructure is fabricated by a three-mask photolithography process with different electroplating processes. This microstructure consists of pads and conductive lines as the bottom layer, Cu-Sn-Ni-Cu pillars with the diameter of 10-40 μm as the middle layer and Cu conductive lines as the top layer. A lift-off process is adopted for the bottom layer. The Cu-Sn-Ni-Cu pillars are fabricated by photolithography with sequential electroplating processes. To fabricate the top layer, a sputtered Cu layer is introduced to prevent the middle-layer photoresist from being developed. With the final Cu electroplating processes, the Cu-Sn-Ni-Cu interconnection microstructure is successfully achieved.

The surface morphology of Cu-Sn pillars consists of densely packed clusters which are formed by an ordered arrangement of tetragonal Sn grains. The diffusion of Cu atoms into the Sn phases is observed at the Cu/Sn interface. Furthermore, the obtained Cu-Sn-Ni-Cu pillars have a flat surface with an average roughness of 13.9 nm. In addition, the introduction of Ni layer between the Sn and the top Cu layers in the Cu-Sn-Ni-Cu pillars can mitigate the diffusion of Cu atoms into Sn phases. The process is verified by checking the electrical performance using four-point probe measurements.

The method described in this paper which combined a three-mask photolithography process with sequential Cu, Sn, Ni and Cu electroplating processes provides a new way to fabricate the interconnection microstructure for future electromigration studies.

As a literature review article, the purpose of this paper is to highlight the intricate interaction and correlation between the interconnection microstructure and the failure mechanism. It is therefore critical to summarize all the challenges in understanding solder solidification of interconnections.

Literature review.

Solidification of solder interconnections is therefore critical because it is the process during which the solder interconnection is formed. The as‐solidified microstructure serves as the starting point for all failure modes. Because of the miniaturization of electronics, the interconnection size decreases continuously, already to such a range that solder solidification takes place remarkably differently from the bulk ingot, on which solidification studies have been focused for decades. There are many challenges in understanding the solidification of tiny solder interconnections, including the complex metallurgical system, dynamic solder composition, supercooling and actual solidification temperature, localized temperature field, diverse interfacial IMC formation, and so on, warranting further research investment on solder solidification.

This paper provides a critical overview of the concerns in solidification study for lead‐free solder interconnection. It is probably an article initiating more attention towards solidification topics.

Traditional chip‐level interconnection materials show many weaknesses given the development trend of microelectronic packaging technology. In order to meet the needs of high‐temperature packaging for wide‐bandgap semiconductors, low‐temperature sintered nano‐silver as a novel semiconductor device‐metallized substrate interconnection material is being developed. One phenomenon that larger interconnection area would cause poor interconnection quality had been found in the industry butut the mechanisms were never previously studied. This paper aims to address these issues.

The changes in the shear strengths and microstructures of nano‐silver joints induced by the changes of interconnection areas were investigated by shear tests and scanning electron microscopy.

The increased interconnection area blocks the organic components to be burnout and causes a higher pore ratio. Thus, it reduces the bonding quality. To ensure a good and steady sintering quality, the interconnection area should be limited to 3 × 3 mm².

A sintering technology or paste with oxygen agent will be studied in the future.

A relationship of shear strength and interconnection area of sintering joints with nano‐silver paste was observed.

The purpose of this paper is to study the intermetallic compound (IMC) thickness, composition and morphology in 100-μm pitch and 200-μm pitch Sn–Ag–Cu (SAC305) flip-chip assemblies after bump reflow and assembly reflow. In particular, emphasis is placed on the effect of solder joint size on the interfacial IMCs between metal pads and solder matrix.

This work uses 100-μm pitch and 200-μm pitch silicon flip chips with nickel (Ni) pads and stand-off height of approximately 45 and 90 μm, respectively, assembled on substrates with copper (Cu) pads. The IMCs evolution in solder joints was investigated during reflow by using 100- and 200-μm pitch flip-chip assemblies.

After bump reflow, the joints size controls the IMC composition and dominant IMC type as well as IMC thickness and also influences the dominant IMC morphology. After assembly reflow, the cross-reaction of the pad metallurgies promotes the dominant IMC transformation and shape coarsened on the Ni pad interface for smaller joints and promotes a great number of new dominate IMC growth on the Ni pad interface in larger joints. On the Cu pad interface, many small voids formed in the IMC in larger joints, but were not observed in smaller joints, combined with the drawing of the IMC growth process.

With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 to150 μm. This work shows that as the packaging size reduced with the solder joint interconnection, the solder size becomes an important factor in the intermetallic composition as well as morphology and thickness after reflow.

The purpose of this paper is to present a novel approach on investigating critical current densities in the solder joints of chip-size surface mounted device (SMD) components. The investigation involves a numerical approach and a physical validation with selected track-to-pad connections and high current loads (CXs).

During the investigations, shape of solder fillets was calculated in Surface Evolver, and then the current densities were calculated accordingly in the given geometry. For the verification, CX tests were performed on joints at elevated temperatures. The joints were qualified with X-ray microscopy, cross-section analysis and shear tests.

This study ascertained that the inhomogeneity in current density depends on the track-to-pad structure of the joint. Also this study found that the heavy CX decreases the mechanical strength, but the degradation does not reach the level of electromigration (EM)-induced voiding.

The heavy CX significantly affects joint reliability and the results point out to EM-induced failure-limitations on printed circuit board (PCB)-based assemblies due to the thermomechanical weakness of the FR4 material.

The experiments investigate current density from a novel aspect on more frequently used small-scale components with different track-to-pad configurations – pointing out possible failure sources.

This paper aims to present a novel approach on investigating critical current densities in the solder joints of chip-size surface-mounted components or device (SMD) components and ball grid array (BGA) lead-free solder joints with the focus of via-in-pad geometries. The investigation involves a numerical approach and a physical validation with selected geometry configurations and high current loads to reveal possible failure sources. The work is a continuation of a previous study.

Current density was investigated using finite element modeling on BGA joints. Dummy BGA components, 0402 and 0603 zero ohm jumper resistors, were used, both in daisy chain setups on standard FR4 printed circuit boards (PCBs). Respective physical loading experiments were set to find effects of elevated current density at hot zones of the joints. Cross-section analysis, scanning electron microscopy and shear force tests were used to analyze the joints.

The findings reveal alterations in the joints, while the current loading is not directly affecting the structure. The modeling reveals the current density map in the selected formations with increased current crowding zones. Overall, the degradation does not reach the level of electromigration (EM)-induced voiding due to the limiting factor of the FR4 substrate.

The heavy current load affects joint reliability, but there are limitations of EM-induced failures on PCB-based assemblies due to the thermomechanical weakness of the FR4 material.

The experiments investigate current density from a novel aspect on frequently used BGA surface mounted components with modeling configurations focusing on possible effects of via-in-pad structure.

This paper aims to study the diffusion of Zn, Ni and Sn in the liquid state during the reflow ageing of the Sn-Zn solder above its melting point on an Ni/Cu substrate in relation to the formation of intermetallic compounds (IMCs).

The Sn-Zn solder is reflowed on Ni/Cu substrates and is aged at 503 K. The formation of IMCs and their composition is characterized using scanning electron microscopy (SEM) and energy-dispersive X-ray spectroscopy (EDX). Diffusion coefficients and diffusion distances of Zn, Ni and Sn in the liquid state during reflow and ageing are theoretically calculated. Both experimental and theoretical behaviours for Ni and Zn diffusions are compared.

Calculations show a linear increment in the liquid-state diffusion coefficients of Ni, Zn and Sn in the solder matrix with a rise in temperature, but they remained constant during ageing. However, diffusion distances increased slowly with temperature but manifold with ageing time. The experimental results revealed segregation of Zn and Ni at the interface in the as-reflow aged specimens. The Zn was concentrated at the solder–substrate interface and it reacted with Ni diffusing from the substrate to form Ni-Sn-Zn IMCs. The rapid diffusion of Zn and Ni with the increase in ageing time increased their atomic concentrations in the IMCs against the reduction in Sn concentration owing to a comparatively slower diffusion.

The novelty of the paper is the detailed study of theoretical diffusion of Zn, Sn and Ni in the liquid state during reflow ageing of Sn-Zn above its melting points on a Ni/Cu substrate. This is compared with values obtained experimentally and related to the mechanisms of IMC formation.

The author proposed a friction plunge micro-welding (FPMW) method and applied it to column grid array packaging to realize the connection of copper columns without precision molds assisted positioning. The purpose of this paper is to study the flow behavior of the solder undergoing frictional thermo-mechanical action during the FPMW and to determine the source of the solders in the micro-zones with different microstructure characteristics near the solder/Cu column friction interface.

Three kinds of Sn58Bi/SAC305 and SAC305/Pb90Sn composite solder samples were designed to study the flow behavior of the solder during FPMW using Bi and Pb as tracer elements.

The results show that most of the solders in the position occupied by the copper column was softened and plasticized during the welding process and was extruded to side of the copper column, flowing axially, circumferentially and radially along a trajectory similar to a conical spiral line. Under the drive of the tangential friction force and the radial hold-tight force, the extruded out visco-plastic solders fully mixed with the visco-plastic solders on the sides of the copper column, and bonded with the solders that deformed plastically on the periphery, so that a stir zone and a dynamic recrystallization zone finally evolved. The outside plastically deformed solders evolved into a thermo-mechanical affected zone.

The flow behavior of the solder during the FPMW was determined, as well as the source of the solders in micro-zones with different microstructure characteristics.

The purpose of this paper is to study the reliability of SnAgCu solder interconnections under different thermal shock (TS) loading conditions.

The finite element method was employed to study the thermomechanical responses of solder interconnections in TS tests. The stress‐strain analysis was carried out to study the differences between different loading conditions. Crack growth correlations and lifetime predictions were performed.

New crack growth data and correlation constants for the lifetime prediction model are given. The predicted lifetimes are consistent with the experimental results. The simulation and experimental results indicate that among all the loading conditions studied the TS test with a 14‐min cycle time leads to the earliest failure of the ball‐grid array (BGA) components.

The paper presents new crack growth correlation data and the constants of the lifetime prediction models for SnAgCu solder interconnections, as well as for the BGA components. The paper adds insight into the thermomechanical reliability evaluation of SnAgCu solder interconnections.

The wearout characteristics were investigated for soldered interconnections of surface mount technology (SMT) chip resistors, chip capacitors and a 44 I/O ceramic leaded chip carrier (CLCC) package. Four double‐sided test vehicles were subjected to accelerated thermal cycling in the — 10°C to + 110°C range; 30°C/min ramp rate; and 1 minute dwell time at each temperature extreme. The test was interrupted at initially 500 cycle and later at 1000 cycle intervals to perform visual inspection of all soldered interconnections, functional performance verification for the test vehicles, and resistance measurement on leaded SMT joints. Metallographic examinations and fractographic studies were also performed after 0, 4500 and 13000 cycles to characterise the micromechanisms of soldered joint strength degradation and failure. The wearout thresholds for soldered joints of chip resistors and capacitors on side 1 were respectively 2500 and 4500 cycles. The greater thermal fatigue resistance of the latter joints was attributed to a lower device‐substrate coefficient of thermal expansion (CTE) mismatch and a more favourable device geometry compared with chip resistors. These passive components on side 2, however, showed a virtually identical soldered joint wearout threshold of 6500 cycles. The constraints imposed by the applied mounting adhesive were primarily responsible for this behaviour. No correlation appeared to exist among various failure criteria used to determine the onset of failure for leaded SMT soldered connections. The concurrent monitoring of electrical resistance and the applied tensile load showed a modest relationship between the load drop and resistance increase, however. The test vehicles continued to pass the functional performance verification, even after 13000 thermal cycles. Nonetheless, the joint wearout thresholds were considered to be 2500, 4500 and 4500 cycles for chip resistor, chip capacitor and CLCC components, respectively. A 50% soldered joint strength drop was considered as the wearout threshold for the CLCC device. Metallographic examination showed limited barrel wall cracking of the vias and no evidence of cracks with the through‐hole soldered joints, even after 13000 thermal cycles.