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The purpose of this paper is to demonstrate the non-destructive methods for detection and localization of interconnection structure discontinuities based on the signal analysis in the frequency and time domain.

The paper deals with the discontinuity characterization of interconnection structures created on substrates used for electronics, and methods for their detection and localization, based on the frequency analysis of transmitted signals. Used analyses are based on the theoretical approach for the solution of discontinuity electrical parameters and are the base for diagnostic methods of discontinuity identification.

The measurement results of reflection parameters, frequency spectrums of transmitted signals and characteristic impedance values are presented on test samples containing multiple line cracks and their width reduction.

Obtained results can be used practically, not only for the detection of transmission lines discontinuities on printed circuit boards but also in other applications, such as the quality assessment of bonded joints.

Developed methods allow the quick identification and localization of particular discontinuities without the destruction of tested devices.

As the speed, density, power dissipation, and overall performance of semiconductor chips continue to improve, electronic equipment designers are finding that their ability to utilise new, high performance ICs is limited by the electrical performance, cost and turnaround time associated with the higher levels of packaging and interconnection. With the evolution of silicon foundries, CAD systems, logic array and standard cell technology, the designer now has the ability to develop and implement custom IC functions rapidly at a fraction of the cost and time associated with full custom IC development. The driving force for this evolution is the need for reduction of product development time and cost. As electronic product life cycles continue to decrease, so must the development time. Although the need to reduce component development times has been acted on first by the semiconductor manufacturers, suppliers of packaging and interconnection components are also feeling the need to provide customised designs rapidly and at low cost. Unilayer II is a discrete wire circuit board technology with a wiring density capability approximating that of multilayer printed wiring boards. However, since the wiring is defined in software and implemented on a numerically controlled wiring machine, the time and cost associated with development, and also with wiring changes, is greatly reduced. This paper presents the results of extensive electrical testing performed to characterise the electrical performance of the discrete wire Unilayer II transmission lines. Characteristic impedance, propagation velocity, capacitance, inductance, and crosstalk are discussed in detail.

The purpose of this paper is to develop a new formulation using spectral approach, which can predict the wave behavior to uncertain parameters in mid and high frequencies.

The work presented is based on a hybridization of a spectral method called the “wave finite element (WFE)” method and a non-intrusive probabilistic approach called the “polynomial chaos expansion (PCE).” The WFE formulation for coupled structures is detailed in this paper. The direct connection with the conventional finite element method allows to identify the diffusion relation for a straight waveguide containing a mechanical or geometric discontinuity. Knowing that the uncertainties play a fundamental role in mid and high frequencies, the PCE is applied to identify uncertainty propagation in periodic structures with periodic uncertain parameters. The approach proposed allows the evaluation of the dispersion of kinematic and energetic parameters.

The authors have found that even though this approach was originally designed to deal with uncertainty propagation in structures it can be competitive with its low time consumption. The Latin Hypercube Sampling (LHS) is also employed to minimize CPU time.

The approach proposed is quite new and very simple to apply to any periodic structures containing variabilities in its mechanical parameters. The Stochastic Wave Finite Element can predict the dynamic behavior from wave sensitivity of any uncertain media. The approach presented is validated for two different cases: coupled waveguides with and without section modes. The presented results are verified vs Monte Carlo simulations.

This paper aims to analyze the negative impact of surface mount (SMT) pad and imperfect via structure such as stub, pad, non-functional pad (NFP) and anti-pad on the signal integrity at 40 Gbps transmission on printed circuit board (PCB) due to impedance mismatch or discontinuity. The optimized modeling of via and SMT structures is performed to achieve minimal impedance mismatch and insertion loss less than 10 dB for six-inch full path transmission line between transmitter and receiver on PCB at Nyquist frequency 20 GHz.

This work is split into two phases. The first phase involves optimization of via and SMT structures in three-dimensional electromagnetic (3DEM) simulation using Hyperlynx Via Wizard and Keysight EMPro software, respectively, followed by analysis of time domain reflectometry (TDR) and insertion loss (Sdd21). Whereas, in the second phase, full path hybrid mode simulation involving vias for signal layer transition, a 6-inch PCB channel and SMT pads is performed using Keysight ADS software to observe the TDR, Sdd21 and eye diagram at 40 Gbps transmission.

Imperfect via and SMT structures have a negative effect on signal reflection and attenuation. The optimized via and SMT minimizes the impedance mismatch by 81 per cent and insertion loss by 4.5 dB, ultimately enlarging the eye diagram opening to achieve minimal data loss at receiver with 40 Gbps transmission.

The results of original empirical research work on signal integrity analysis that optimizes the PCB channel design to achieve 40 Gbps signal transmission are presented in this study. It serves as a reference guide for high-speed PCB layout design.

The once highly publicised Porcelain Enamelled Steel (PES) substrates seem to have disappeared from the public gaze, or have they? They certainly have not. If anything, they have consolidated their place in electronics applications and are growing in use at a remarkable pace in particular applications supplied by the major USA source, namely Ferro‐ECA.

This paper aims to analyze the impact of non-perfect reference plane on the integrity of microstrip differential signals at multi-gigabit transmission on a printed circuit board (PCB). The effects of non-perfect reference contributed by signal crossing over split plane such as impedance discontinuity and crosstalk are investigated by performing analysis in two phases.

The first phase involves three-dimensional electromagnetic modeling extraction using Keysight EMPro software. Meanwhile, the second phase involves the import of model extracted from EMPro into simulation using Keysight Advanced Design System that covers insertion loss, return loss, crosstalk, time domain reflectometry and eye diagram.

A non-perfect reference plane has a negative impact on signal reflection, attenuation and crosstalk. The analysis results are presented and discussed in detail in the later section of this paper.

The work that studied the impact of the width and the amount of gaps due to crossing of split planes being experienced on the signal integrity was performed by other researchers. Meanwhile, this paper focused on the impact of length and depth of the gap on signal integrity. These research papers serve as a reference guide for high-speed PCB layout design.

This paper presents the results of research into the process of testing controlled impedance circuit boards. It aims to provide a general introduction to the subject of controlled impedance circuit board production for manufacturers wishing to make this type of board in the future and offers constructive suggestions for those who may want to improve on their current process. Consequently, in addition to describing test issues there are references to some of the other main subject areas that require attention when the production of high quality controlled impedance circuit boards is to be considered, namely design, materials and fabrication. The content of this paper is based on production trials that were conducted by MEPD Met‐Etch (Selkirk) Ltd at their manufacturing facilities in Scotland as part of a UK Ministry of Defence research contract. The results of this research were included in a report for the UK Defence Research Agency (Electronics Division) and subsequently were also detailed in an individual ‘Guidelines for Designers’ document. This document has since been separately submitted to ECL 19 with a view towards incorporation into the CECC 23000 Approval System. In order to verify the test results, separate comparison measurements were also conducted by other circuit board manufacturers using a range of suitable test instrumentation. There is a growing requirement in the printed circuit board industry for a simple means of testing controlled impedance boards. This paper promotes the use of computer‐controlled test instrumentation so that accurate and repeatable measurements can be made by production staff in a manufacturing environment. If this is achieved, it should be possible to close the quality loop on controlled impedance circuit board production using normal statistical process control techniques.

The purpose of this paper is to clarify the method of using RF impedance changes as an early indicator of degradation of solder joint. It proposes the mode of crack propagation in solder joint and outlines why RF impedance analysis can be capable of detecting small cracks. The study aims to show the potential of RF impedance analysis as a prognostic tool that can provide advanced warning of impending failures of solder joint.

In this paper, the mode of crack propagation in solder joint was studied to show why RF impedance analysis could be capable of detecting small cracks. A real simple impedance‐controlled test vehicle was developed to allow RF impedance and DC resistance measurements to monitor solder joint degradation. The influence of crack length on RF impedance was evaluated by high frequency structure simulator (HFSS) simulation for the first time.

The paper demonstrates that RF resistance can respond to an open state of a solder joint as well as DC resistance. Furthermore, RF impedance can monitor partial degradation of solder joints, while the DC resistance cannot do it. In addition, time‐domain reflection coefficient is found to be more useful than RF impedance in detecting solder joint degradation. The HFSS simulation results show that even very slight physical degradation of solder joints can be detected using RF impedance analysis.

In this paper, HFSS simulation is used for the first time to evaluate the influence of crack length on RF impedance.

A new time‐domain reflectometry measurement method is described that provides accurate measurements of the average high‐frequency (0.1GHz ‐ 10GHz) dielectric constant of printed wiring board materials and is suitable for “factory floor” use. A parallel‐plate transmission line is used for the sample geometry. Only simple numerical processes are required to extract the characteristic impedance and dielectric constant of the sample from the acquired data. The long‐term measurement reproducibility and short‐term measurement repeatability of the method are described.

High‐density interconnect (HDI) continues to be the fastest growing segment of the printed circuit board (PCB) market. The purpose of this paper is to discuss the differences in designing HDI compared to conventional PCB multilayers. This is important for the challenging aspects of very high‐speed electronics that require care to control signal integrity and power integrity.

Eight new design principles were studied and illustrated with emphasis on how these differ from conventional PCB design.

HDI implementation can be improved 2X to 4X by employing these new design principles. Densities from 6‐12 in. per sq. inch to 18‐48 in. per sq. inch have been reported. Design time reductions of 50 percent and cost reductions of 30 percent were also seen.

This work was focused on the basic design principles and does not address electronics design automation tools or specific design steps. PCB design is a complex activity and readers are encouraged to obtain and use the references cited.

The paper describes various design and layout procedures that the authors have learned over the last 29 years involved in printed circuit design and fabrication. These principles can be combined with other innovations to enable a much more beneficial use of HDI technologies.