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In the competitive global market, firms have to keep profit from innovation activities. A firm makes profits by offering products or services at a lower cost than its competitors or by offering differentiated products at premium prices that more than compensate for the extra cost of differentiation. The IC Package and Testing technology industries were the first high technological industry to build in Taiwan. The Package and Testing industries in Taiwan adopted competitive innovation activities to become stronger. In our study, we want to know how innovation activities influence a firm operating in the IC Package and Testing industries. Our study used a questionnaire and Likert five‐point scale to survey the innovation activities, customer and feedback in innovation performance in the IC Package and Testing industry. The wafer level chip size packing technology in our study indicates the innovation activities. Because we need to compare the difference between the wafer level chip size packing technology and wire bonding technology to recognize innovation and how the innovator and customer were influenced. Our conclusions are described below: (1) When the innovator adopts innovation activities that can be maintained using experiments and knowledge, using machine and decision variables more quickly will produce success; (2) Innovators should adopt innovation activities that focus on customers that use knowledge and experimentation, training time and cost. If an innovation forces customers to spend much time and cost to learn new technology or applications, the innovation will not be adopted; (3) Innovators that create innovation performance higher than his customers must also consider the impact upon their customers. We have to remind innovator to focus on why their customers have a different level of evolution in the same innovation activities.

When designing electronic systems it is very useful to analyse the relationship between the interconnection capacity of selected packaging methods and their prices. Such an analysis is provided for the entire gamut of the interconnection spectrum: from one‐sided PCBs to complex ICs, by a plot of the log of substrate price/sq. inch versus the log of substrate density expressed in inches of conductors/sq. inch of substrate. The use of such a graphic method of analysis can produce interesting and useful insights into the potentials and tradeoffs between various current and future IC packaging approaches. After a short description and analysis of that log‐log plot, this paper will apply this methodology to the derivation of the general cost relation of IC interconnections on the next level of substrates. It specifically will attempt to establish a general price relationship between packaging approaches using bare (uncased) chips and the chips packaged in individual packages. As a result, the cost‐effectiveness of the use of Multi‐chip Module technology in the regions of very high interconnection densities will be derived and its competitiveness against other interconnection methods will be analysed.

The concept of packaging integrated circuits while they are still in wafer form has captured the imagination of semiconductor manufacturers and packagers around the globe. One such concept, referred to as wide area vertical expansion (WAVE^TM) technology promises to provide a relatively easy method for cost effectively interconnecting ICs while still on the wafer. Moreover the fundamental technology is amenable to the production of “virtual wafers” where individual IC chips can be assembled en masse. The virtual wafer variation also allows for die shrink to occur, while the IC package footprint remains constant. The technology is based on concepts that allow for the mass assembly and production of compliant packages both directly on the wafer and in “virtual wafer” format where individual chips are bonded directly to the flexible pellicle. This paper examines this important new packaging technology concept in terms of the process and device and the implications and future directions the technology is likely to take.

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

The paper's findings will be very useful to the electronic industry.

To determine the status of internet and e‐commerce adoption by the Taiwan semiconductor industry, the research is designed to help government and enterprise in formulating strategic plans and making resource allocation decisions.

Using the three‐level model of internet commerce adoption (MICA), a survey of 287 companies and web sites was designed. Semiconductor firms were placed into five categories: integrated circuit (IC) design, manufacturing, packaging, IC testing, and peripheral device manufacturing.

The MICA model shows the internet adoption ratio for semiconductor firms as 82.6 percent, significantly higher than the electronics and electrical machinery industry sector (56.5 percent). The IC manufacturing and packaging segment are in the processing stage, the final stage of development for the MICA model. One‐third of the IC testing industry segment falls into the provision stage, and 36.1 percent web sites are in the processing stage. The IC design and peripherals industrial segments are located in the provision stage.

The IC manufacturing segment is conducting more financial transactions than the other segments – a result that matches earlier research showing that larger companies are most likely to implement e‐business applications. Many enterprises in the industry are lagging with the adoption of the internet indicating a need for education and training.

This benchmark study provides a framework for evaluating the internet adoption status of semiconductor and other high technology firms. The MICA model is demonstrated to be suitable for evaluating the different stages of internet adoption.

Known good die, flip chip and chip scale packages are technologies that offer various advantages to the board manufacturer. A discussion of the different types of package options, their methods of assembly, test and performance comparisons can help to resolve the general direction a manufacturer might pursue for next generation systems. This paper attempts to give a perspective as well as highlighting the areas of concern with the different options.

Multichip modules using lamination techniques to make the substrate (MCM‐Ls) are a natural extension of printed circuit technology to meet the ever increasing demands of system integration and density. As with other forms of MCM, the interconnection density is so high that many circuits need only two signal layers. The substrate can also incorporate layers to control thermal expansion and extract heat. MCM‐L substrates are extraordinarily versatile; they can accommodate packaged ICs (e.g., fine pitch SMT), unpackaged ICs, other MCMs and odd‐form components. There is a large and growing number of MCM‐L suppliers offering solutions for a wide range of sizes, complexities, performance and market sectors at competitive prices.

In future generations, electronic systems will rely extensively on advanced IC technology to achieve higher performance levels. However, with limits placed on the level of integration that can be obtained on a single IC, a need still exists for an interconnection hierarchy to provide the necessary density transform between system components. A recent addition to many high performance interconnection structures has been the Multichip Module. By eliminating the conventional IC package, MCMs have dramatically reduced the electrical length between devices, thereby minimising propagation delay, crosstalk, and attenuation. Although MCM techniques will offer many performance advantages, they also present many design challenges at subsequent levels of interconnection. This paper will focus on the requirements of MCM backplanes interconnecting several modules and, as a solution, will present recent work on advanced metal core substrates. MCM substrates provide a tremendous density advantage, however, the interconnection between modules is still a formidable task. Modules often have I/O densities of 300 to 500 leads per square inch and typically dissipate 10 to 50 watts per square inch. In addition, with sub‐nanosecond rise times, the distance between modules is often sufficient for signal paths to be treated as transmission lines. In an effort to meet these requirements, metal core circuits based on copper, copper Invar, and copper molybdenum have been fabricated using 0·0025 in. diameter embedded discrete wiring technology. Combined with a Kevlar surface layer suitable for wire bonding and blind laser drilled vias to access the internal wires, this technique offers many benefits. As many as 4 conductors can pass between holes on 0·050 in. centres in a single wiring layer only 0·018 in. thick. With the absence of interstitial vias, additional substrate area can be dedicated to create a sizeable thermal path, essential to conduct the heat from the MCM to an internal metal core. Together, these features have made this an attractive approach for interconnecting multichip modules.

Flexible circuits are ideally suited to solving the design demands of next generation electronics. The flexible circuit offers a number of advantages that are unavailable to those using more traditional, rigid type interconnection structures. A number of new applications for flexible circuits have been developed that may well provide a glimpse of what is yet to come in electronic packaging technology. These new applications embrace the whole spectrum of the electronics interconnection world from chip packaging to high density multilayer structures. Reviewed here are some of the more novel uses of the flex circuit for high performance electronic interconnection.