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This paper developed a new method of making floor from poplar using glued technology and densification technology. This paper aimed to use fast-grown poplar wood to produce floor to expand material supply range of floor in order to solve problem of material supply shortage for floor industry.

Densification technology and gluing technology were used to obtain high-density surface materials of floor under high pressure, meanwhile in order to reduce loss of poplar wood caused by compressing, high-density surface materials floor and substrate are glued and pressed under low pressure.

The method of compressing poplar wood under high pressure can improve poplar's physical and mechanical properties. Adopting densification technology and gluing technology can produce the poplar laminated composite floor which meets the requirements of Chinese standard GB/T 18103.

This method of producing floor by compression densification technology would cause wood loss from reduction in thickness because poplar was pressed under high pressure.

This method of making floor from poplar wood concerned in this study allows the floor making industry to eliminate its dependence on precious wood resource, expand supply range of floor material, and then solve problem of wood supply shortage of floor industry.

This study may help solve the difficult problem that poplar cannot directly be used to produce floor because of its softness, low density and low strength. Through densification technology, great improvement in strength and hardness of poplar had been made.

Rigid multilayer polyimide printed wiring boards exhibit unusually large dimensional change during the lamination process. Therefore, the use of large polyimide multilayer panels for high density circuitry is often limited. This study examined ten probable causes for dimensional instability and how each affected the shrinkage/growth in the laminated panel. The report shows that a combination of methods and materials can reduce the resultant dimensional change experienced during lamination from 0·001 inch/inch to less than 0·0002 inch/inch in planar directions.

A developmental project has been initiated to create a new type of glass fabric, whose fibers are to be uniformly distributed in the laminate so as to comply with the requirement of homogeneity. As a result, various types of glass fiber fabrics have successfully woven through the uniquely developed “MS process”, and it has been verified that each of the glass fabrics possesses the most suitable structure to attain uniform distribution in the laminates. The laminates, using the newly developed glass fabrics, have proved that the micro‐diameter drilling, that is laser drilling and mechanical drilling with 0.1mm diameter, can be performed very easily with less drill bit breakage, and produces uniform drill holes. It has also been proved that the laminates with the new glass fabrics reveal improved mechanical properties such as lower CTE, decreased warp and twist and better dimensional stability compared with conventional laminates of glass epoxy. Various styles of new glass fabric cover the wide range of thickness from 100 microns down to 27 microns.

While promising significant improvements in the cost and performance of electronic systems, the advent of new area array packaging concepts such as the BGA and newer area array CSPs has placed significant new demands on the substrates used in their interconnection. New methods such as build‐up multilayers and micro vias and co‐lamination of inner layers have been described and implemented by a number of different firms in an attempt to address this important issue. One such method employs simple double‐sided plated through hole flex circuits and the use of conductive pastes and bondplies to provide reliable electrical and mechanical connection between layers during a simple lamination cycle. The process, briefly described herein as a co‐laminated multilayer flex, is detailed in terms of both process steps and manufacturing flow. The structure of the interconnection substrate is also modeled and examined to determine its electrical performance potential according to electrical modeling software. Finally, detailed are the performance of the structure in reliability testing and an analysis of the expected design and performance advantages that might be obtained by such type constructions in combination with BGAs and area array CSPs.

A novel interconnect technology, introducing thin film on a laminate substrate base, is presented. A specially constructed laminate board is used as a substrate for the thin film build‐up process. The main characteristics of the laminate core substrate are the z‐axis electrical connections, the absence of holes in the substrate and the very flat nature of the top surface. As a result, the base substrate can be processed further in a thin film processing line. The manufacturing and properties of these substrates are discussed.

The ChemicalVia process, patented by CERN, provides a new method of making microvias in high‐density multilayer printed circuit boards of different types, such as sequential build‐up (SBU), high density interconnected (HDI), or laminated multi‐chip modules (MCM‐L). The process uses chemical etching instead of laser, plasma or other etching techniques and can be implemented in a chain production line. This results in an overall reduced operation and maintenance cost and a much shorter hole production time as compared with other microvia processes.

Laminated substrates are used widely in the manufacture of multichip modules (MCM‐L) by the electronic packaging industry. Of late, the thrust has been towards higher density circuitry to achieve improved performance and reduced size. This has led to the use of finer lines and spacings, smaller drilled holes and buried vias in organic laminates leading to reliability issues such as electrochemical migration. One of the forms of electrochemical migration is known as conductive filament formation. Conductive filament formation is an electrochemical process. In accelerated environments of temperature and humidity, organic laminates can develop a loss of insulation resistance between conductors, eventually resulting in loss of electrical function of the circuit. The paper aims at discussing electrochemical migration in general, and conductive filament formation in particular, and its impact on the reliability of MCM‐L.

The purpose of this paper is to discuss the use of epoxy‐based conducting adhesives in z‐axis interconnections.

A variety of conductive adhesives with particle sizes ranging from 80 nm to 15 μm were laminated into printed wiring board substrates. SEM and optical microscopy were used to investigate the micro‐structures, conducting mechanism and path. The mechanical strength of the various adhesives was characterized by 90° peel test and measurement of tensile strength. Reliability of the adhesives was ascertained by IR‐reflow, thermal cycling, pressure cooker test (PCT), and solder shock. Change in tensile strength of adhesives was within 10 percent after 1,000 cycles of deep thermal cycling (DTC) between −55 and 125°C.

The volume resistivity of copper, silver and low‐melting point (LMP) alloy based paste were 5 × 10⁻⁴, 5 × 10⁻⁵ and 2 × 10⁻⁵ Ω cm, respectively. Volume resistivity decreased with increasing curing temperature. Adhesives exhibited peel strength with Gould's JTC‐treated Cu as high as 2.75 lbs/in. for silver, and as low as 1.00 lb/in. for LMP alloy. Similarly, tensile strength for silver, copper and LMP alloy were 3,370, 2,056 and 600 ψ, respectively. There was no delamination for silver, copper and LMP alloy samples after 3X IR‐reflow, PCT, and solder shock. Among all, silver‐based adhesives showed the lowest volume resistivity and highest mechanical strength. It was found that with increasing curing temperature, the volume resistivity of the silver‐filled paste decreased due to sintering of metal particles.

As a case study, an example of silver‐filled conductive adhesives as a z‐axis interconnect construction for a flip‐chip plastic ball grid array package with a 150 μm die pad pitch is given.

A high‐performance Z‐interconnect package can be provided which meets or exceeds JEDEC level requirements if specific materials, design, and manufacturing process requirements are met, resulting in an excellent package that can be used in single and multi‐chip applications. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.

A new treatment method for the copper innerlayers of polyimide multilayer printed wiring boards has been developed. Conventional oxide coatings experience acid penetration through the bonding interface during through‐hole plating pretreatment. This problem was eliminated by substitution of metallic copper for the surface oxide. Promotion of the copper innerlayer adhesion to the prepreg by the oxide coating was based upon a mechanical interlocking effect caused by the minute roughness of the oxide crystals. Reduction treatment of the surface oxide layer was found to give a metallic copper surface with no changes in its morphology. Adhesion strength of polyimide prepregs to copper foils after the reduction treatment was equivalent to that of the original brown oxide coating. Acid resistance was enhanced by elimination of the oxide layer from the bonding interface. The reduction treatment, combined with the conventional oxide coating technique, can realise high density multilayer printed wiring boards with greater reliability and performance.

Flex‐rigid circuits have been used for many years, primarily by the military, as a method to reduce the size and increase the reliability of electronic systems. However, in today's emerging designs where high speed ASICs are often the dominant components, flex‐rigid circuit assemblies are now an attractive solution for providing high density transmission line interconnects from board to board. Much of today's circuitry is being committed to ASIC designs to increase both circuit density and speed. Following this path, designers are faced with the task of interconnecting high lead count SMT packages often with as many as 300 to 500 leads per device, each dissipating several watts. At these power densities conductive cooling through the circuit board is often a necessity, dictating the use of either metal cores or heat exchangers. To make efficient use of the core and minimise weight, designs generally require SMT packages to be mounted on both sides of the core with electrical communication from side to side. However, as more exotic core materials (carbon fibre matrix, beryllium, etc.) and liquid cooled heat exchangers are used, electrical communication through the core has become difficult, if not impossible, in some cases. Instead, high density flex‐rigid assemblies are used to partition the circuit, allowing the board to ‘fold’ over the core. This results in hundreds of signal lines that must cross the flex, obeying the electrical design rules dictated by the rigid sections to maintain impedance values and crosstalk margins. This paper focuses on recent work at AIT, producing high density flex‐rigid circuits using embedded discrete wiring technology to meet the above requirements. Using 0.0025 in. diameter polyimide insulated wire, as many as 100 lines per linear inch can pass over the flex region on a single layer. This generally results in a single flex layer where all wires can be referenced to a continuous ground plane from board to board. Controlled impedance is easily maintained due to the uniform wire geometry, and high frequency attenuation is significantly lower than on equivalent etch circuit designs due to the smooth surface finish on the wire. In addition, the high interconnection density offered by this technique reduces the overall thickness of the rigid sections, thereby minimising the thermal resistance to the core.