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In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications.

The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit.

The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased.

The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

At first, the organic/inorganic and hybrid PV materials by their electrical model are described. Then the proposed converter topology, circuit analysis and various operating modes of converter according to on/off timing of switches are investigated. The current and voltage in the converter components are illustrated and the voltage gain and switching stress of proposed converter are presented. Finally, to show the effectiveness of the proposed converter, the power loss analysis is provided and the simulation is done in PSIM software. In the last section, the advantages of the proposed topology of higher efficiency by lower number of components in compare with other conventional topologies are presented.

In this paper, an improved topology of DC-DC converter based on VL technique is proposed for Perovskite Solar cells (PeSCs). The PeSCs attracted a lot of interest due to their potential in combining the advantages of both organic and inorganic components. The proposed converter by using fewer components and higher output voltage generation in compare with conventional ones could be a good candidate for PeSCs due to lower efficiency of this cells. The performance of converter is expressed in continuous conduction mode (CCM) and discontinuous conduction mode (DCM), and the boundary conditions for the proposed converter is presented.

By using VL technique, this converter is used to boost the lower output voltage levels of PeSCs for grid connection. The PV cell output voltage is increased from 24.5 V to 106 V by proposed converter topology. The step-by-step voltage increasing by charging and discharging of inductor and capacitor is used for boosting the input voltage. By comparing other converters, there is no design complexity in the proposed converter structure, and the power loss is much reduced which increases the converter efficiency. On the other hand, due to using lower number of elements of energy storage elements such as inductors and capacitors, the converter cost is also diminished. Therefore, the design topology simplicity which result simple control algorithm and lower number of components which diminish the system cost by appropriate voltage boosting capability are the main advantages of this proposed topology for new PeSCs which don’t have enough efficiency in compare with old Si PV cells.

In this paper, by using the lower number of components a new structure of DC-DC converter based on the VL technique is proposed. The advantages of this converter such as the simplicity, easier control and high voltage gain by lower power loss, could make this converter a good candidate for new PeSCs where the system whole efficiency will be a critical point to have the unique properties of this new materials in lower loss.

Multilevel inverter (MLI) is an established design approach for inverter applications in medium-voltage and high-voltage range of applications. An asymmetric design synthesizes multiple DC input voltage sources of unequal magnitudes to generate a high-quality staircase sinewave comprising a large number of steps or levels. However, the implications of using sources of unequal magnitudes results in the requirements of a large variety of inverter switches and higher magnitudes of the total blocking voltage (TBV) rating of the inverter, which increase the cost. The purpose of this study is to present a solution based on algorithms for establishing DC source magnitudes and other design parameters.

The approach used in this study is to develop algorithms that bring an asymmetric cascaded MLI (ACMLI) design close to symmetric design. This approach then reduces the variety of switch ratings and minimizes the TBV of the inverter. Thus, the benefits of both asymmetric design (generation of a large number of voltage levels in the output waveform) and symmetric design (modularity) are achieved. The proposed algorithms can be applied to a number of ACMLI topologies, including classical cascaded H-bridge (CHB). The effectiveness of the proposed algorithms is validated by simulation in Matlab-Simulink and experimental setup.

Two new algorithms are proposed that reduce the number of variety of switches to just three. The variety can further be reduced to two under a specified condition. The algorithms are compared with the existing ones, and the results are promising in minimizing the TBV rating of the inverter, which results in cost reduction as well. For a specific case of four CHBs, the proposed Algorithm-1 produced 27% and Algorithm-2 produced 53% higher levels. Moreover, the presented algorithms produced minimum values of the TBV and resulted in minimum cost of inverter.

The proposed algorithms are novel in structure and have achieved the targeted values of minimized switch variety and reduced TBV ratings. Due to less variety, the inverter achieves a near symmetric design, which enables to attain the added advantages of modularity and reduced difference of power sharing among the DC sources.

How to use a simple and classical topology to provide a high-efficiency excitation voltage for dielectric barrier discharge (DBD) loads is one of the primary problems to be solved for DBD application fields.

To address the issue, a set of modes that can generate a high-efficiency pulse excitation voltage in a full-bridge inverter are adopted. With the set of modes, the unique equivalent circuit of DBD loads and the parasitic parameter of the step-up transformer can be fully used. Based on the set of modes, a control strategy for the full-bridge inverter is designed. To test the performance of the power supply, a simulation model is established and an experimental prototype is made with a DBD excimer lamp.

The simulation and experimental results show that not only a high-efficiency excitation voltage can be generated for the DBD load, but also the soft switching of all power switch is realized. Besides this, with the set of modes and the proposed control strategy, the inverter can operate in a high frequency. Compared with other types of power supplies, the power supply used in the paper can fully take advantage of the potential of the excimer lamp at the same input power.

This work considers that how to use a simple and classical topology to provide a high-efficiency excitation voltage for DBD loads is one of the primary problems to be solved for DBD application fields.

The purpose of this paper is to investigate how the dc-link voltage for the converter of a wind generator should be selected, i.e. to determine the losses in the generator and the converter when using various dc-link voltage levels.

To presents the efficiency evaluation of 5 MW wind turbine generating systems, two 5 MW surface mounted permanent magnet synchronous generators (PMSG) with medium and low rated voltage is designed. A two-level transistor converter is considered for ac/dc conversion. Three different dc-link voltage levels are used. By using these voltage levels the PMSG is utilized in slightly different ways.

It is found that the system with the lower voltage machine has slightly higher annual energy efficiency compare to the higher voltage system. Furthermore, it is shown that the best choice for the dc-link voltage level is a voltage between the minimum voltage which gives the desired torque and the voltage which gives Maximum Torque Per Ampere.

A procedure as well as investigations with quantified results on how to find the highest complete drive system efficiency for a wind turbine application. Based on two given PMSG, the most energy-efficient dc-link voltage has been established.

To derive an analytical model for a dc‐ac‐dc parallel resonant converter operating in lagging power factor mode based on the steady‐state operation conditions and considering the effects of a high‐frequency transformer.

A range of published works relevant to dc‐ac‐dc converters and their control methods based on pulse‐width‐modulation technique are evaluated and their limitations in output measurement of higher output voltage converters are indicated. The circuit diagram of the converter is described and the general mathematical model of the system is obtained by deriving and combining the mathematical models of the different converter blocks existing in the system. The derived mathematical model is used to study the steady‐state and transient performance of the converter. The deriving procedure of the analytical model for a parallel resonant converter is extensively given and the analytical model obtained is verified by simulation results achieved using MATLAB/SIMULINK and the program written by the authors.

The paper suggests an analytical model for dc‐ac‐dc parallel resonant converters. The model can be used in the output voltage estimation of a converter in terms of its phase‐shift angle and the dc‐link voltage.

The resources in the library of the authors' university and also the English resources relative to dc‐ac‐dc converters reachable through the internet were researched.

The analytical model suggested can be used in estimating the output voltage of the converters used in high‐voltage applications or where there are difficulties in employing sensors in measurement of the output voltage due to high price or implementation problems.

The originality of the paper is to present an analytical model for dc‐ac‐dc parallel resonant converters. Using this model makes it possible to estimate the output voltage of the converter using the dc‐link voltage and the phase‐shift angle. The proposed model provides researchers to regulate the output voltage of the converters using feed‐forward control technique.

The purpose of this study was to design, fabricate and test devices based on transformers integrated with low-temperature co-fired ceramic (LTCC) modules with isolation between primary and secondary windings at the level between 6 and 12 kV.

Insulating properties of the LTCC were examined. Dielectric strength and volume resistivity were determined for common LTCC tapes: 951 (DuPont), 41020, 41060 (ESL), A6M (Ferro) and SK47 (KEKO). According to the determined properties, three different devices were designed, fabricated and tested: a compact DC/DC converter, a galvanic separator for serial digital bus and a transformer for high-voltage generator.

Breakdown field intensity higher than 40 kV/mm was obtained for the test samples set, whereas the best breakdown field intensity of about 90 kV/mm was obtained for 951 tape. The materials 41020 and 951 exhibited the highest volume resistivity. Fabricated devices exhibited safe operation up to a potential difference of 10 kV, limited by minimum clearance. Long-term stability was assured by over 20 kV strength of inner dielectric.

This paper contains description of three devices made in the LTCC technology for application in systems with high-voltage isolation requirement, for example, for power or railway power networks.

The results show that LTCC is a suitable material for fabrication of high-voltage devices with integrated passives. Technology and properties of three examples of such devices are described, demonstrating the ability of the LTCC technology for application in reliable high-voltage devices and systems.

As it is known, the electrostatic discharge (ESD) protection design of integrated circuit is very important, among which the silicon controlled rectifier (SCR) is one of the most commonly used ESD protection devices. However, the traditional SCR has the disadvantages of too high trigger voltage, too low holding voltage after the snapback and longer turn-on time. The purpose of this paper is to design a high-performance SCR in accordance with the design window under 0.25 µm process, and provide a new scheme for SCR design to reduce the trigger voltage, improve the holding voltage and reduce the turn-on time.

Based on the traditional SCR, an RC-INV trigger circuit is introduced. Through theoretical analysis, TCAD simulation and tape-out verification, it is shown that RC-INV triggering SCR can reduce the trigger voltage, increase the holding voltage and reduce the turn-on time of the device on the premise of maintaining good robustness.

The RC-INV triggering SCR has great performance, and the test shows that the transmission line pulse curve with almost no snapback can be obtained. Compared with the traditional SCR, the trigger voltage decreased from 32.39 to 16.24 V, the holding voltage increased from 3.12 to 14.18 V and the turn-on time decreased from 29.6 to 16.6 ns, decreasing by 43.9% the level of human body model reached 18 kV+.

Under 0.25 µm BCD process, this study propose a high-performance RC-INV triggering SCR ESD protection device. The work presented in this paper has a certain guiding significance for the design of SCR ESD protection devices.

This study aims to propose a mathematical model for stacked multicell converters (SMCs), to be exploited in the analytic determination of natural voltage balancing dynamics of the flying-capacitor (FC) stacked multicell multilevel converters, i.e. investigations of the start-up behavior, dynamic response, and natural voltage balancing phenomenon.

The crux of the proposed strategy is based on the closed-form analytic solution derivation for the switching functions used in the switching of the SMCs operated under phase disposition (PD) and phase shifted carrier (PSC) pulse width modulation (PD-PSC-PWM) technique. Hence, the suggested approach develops an analytic solution for the Fourier series and associated Fourier coefficients pertinent to the switching functions of the SMCs by obtaining the switching instants of the PD-PSC-PWM modulator in terms of Kapteyn series when the frequency of the triangular carrier waveform (fc) and that of the sinusoidal reference waveform (fr) have an integer ratio, i.e. f _c  · f _r −1=k, k∈N.

This approach results into a model, first order differential equation based model, which can be readily developed for the SMCs with any number of levels expediting the investigation of their performance. Furthermore, by an experimental scrutiny conducted on a 4×2-cell-nine-level topology of an SMC, it is inferred that under PD-PSC-PWM modulation technique, FC voltages balance naturally for higher number of stacks and cells, therefore the natural balancing exist for high-level SMCs.

Despite the sophistication of the proposed methodology and mathematical model, this study presents an alternative approach with high potential of applicability for derivation of the multilevel converter mathematical model exploiting the Kapteyn (Bessel-Fourier) series.

Numeric computation results of the proposed analytic model for the SMCs and the simulation results as well as investigational measurements taken from 2×2-cell-five-level and 4×2-cell-nine-level experimental set-ups are presented in order to substantiate the suggested approach, derived model, and verification of natural balancing.

This article and its innovations are original.

This paper is devoted to the quasi‐Z‐source (qZS) converter family. Recently, the qZS‐converters have attracted high attention because of their specific properties of voltage boost and buck functions with a single switching stage. As main representatives of the qZS‐converter family, this paper aims to discuss the traditional quasi‐Z‐source inverter as well as two novel extended boost quasi‐Z‐source inverters.

Steady state analysis of the investigated topologies operating in the continuous conduction mode is presented. Input voltage boost properties of converters are compared for an ideal case. Mathematical models of converters considering losses in components are derived. Practical boost properties of converters are compared to idealized ones and the impact of losses on the voltage boost properties of each topology is justified. Finally, the impact of losses in the components on the boost conversion efficiency is analyzed.

To demonstrate the impact of component losses on the overall efficiency of the qZS‐converter, a number of experiments were performed. The impact of inductor winding resistance was compared with the forward voltage drop of qZS‐network diodes. It was found that the forward voltage drop of diodes has the highest effect on the efficiency. If the diodes are replaced with high‐power Schottky rectifiers with a low forward voltage drop (UD=0.6 V), the effective efficiency rise by at least 5 percent could be expected for all three qZS‐converter topologies. For the same operating parameters and component values, the traditional qZS‐converter had the highest efficiency of the qZS‐converter family. The boost converter was compared with the traditional qZS converter in terms of efficiency. It was found that the boost converter has an efficiency 2 percent higher in the boost operation mode and approximately the same efficiency in the non‐boost operation.

The paper provides a good theoretical background for further practical studies. qZS‐converters have voltage boost and buck functions with a single switching stage, which could be especially advantageous in renewable energy applications.

The paper presents a detailed study of the qZS‐converter family. Mathematical models of converters considering losses in components are derived. It is the first time the boost converter is compared with the qZS converter.