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This paper describes a process for fabricating high density multilayer polyimide‐metal interconnect structures for packaging applications such as multichip carriers, flex circuits and multiconductor TAB tape. The process combines the advantages of a semi‐additive via process, such as the uniformity of the electroplated vias and the ability to produce vertical stacked‐up vias, with a processing sequence that does not require a temporary plating mask for vias or a planarisation/via‐top‐exposure step. The key idea behind the process is the fact that all of the circuitry in a multilayer interconnect is electrically connected to the upper conductor layer. This allows building the interconnect upside down on a temporary substrate using a continuous bottom level metallisation as an electrode for plating all level vias. This layer eventually becomes the upper conductor. After the processing is complete, the multilayer interconnect structure is either released from the temporary substrate, resulting in a multilevel multichip interconnect. After the multilevel structure is released, the continuous metal, which was on the bottom, is patterned with the upper conductor pattern, isolating the individual circuits. As an example, a process sequence for building a three‐metal‐layer substrate with 5 ?m by 30 ?m copper conductors, 50 ?m by 50 ?m square vias with 15 ?m interlayer polyimide is presented along with electrical test data. The process can be extended to producing mixed‐geometry multiconductor tape structures for TAB that result in tape frames with controlled conductor properties, and offer the potential for finer geometries for TAB fingers than are now available through conventional TAB tape processes.

When designing electronic systems it is very useful to analyse the relationship between the interconnection capacity of selected packaging methods and their prices. Such an analysis is provided for the entire gamut of the interconnection spectrum: from one‐sided PCBs to complex ICs, by a plot of the log of substrate price/sq. inch versus the log of substrate density expressed in inches of conductors/sq. inch of substrate. The use of such a graphic method of analysis can produce interesting and useful insights into the potentials and tradeoffs between various current and future IC packaging approaches. After a short description and analysis of that log‐log plot, this paper will apply this methodology to the derivation of the general cost relation of IC interconnections on the next level of substrates. It specifically will attempt to establish a general price relationship between packaging approaches using bare (uncased) chips and the chips packaged in individual packages. As a result, the cost‐effectiveness of the use of Multi‐chip Module technology in the regions of very high interconnection densities will be derived and its competitiveness against other interconnection methods will be analysed.

This paper addresses three main technologies of large scale interconnects that have been evaluated at the Microelectronics Department of Crouzet Aerospace for chip and wire or LCCCs (Leadless Ceramic Chip Carriers). The P/I (Packaging and Interconnect) structures that will be discussed are either ceramic multilayer with MLTF multilayer thick film, and CMC (Cofired Multilayer Ceramic) or advanced PWBs. The paper will present the R&D that has been carried out on MLTF and advanced PWBs and the evaluation programme now in progress for CMC. Test results are given, technology status and next generation interconnects are described and some aerospace applications are presented.

This paper aims to investigate the microstructural evolution rules of the intermetallic compound (IMC) layers in high‐density solder interconnects with reduced stand‐off heights (SOH).

Cu/Sn/Cu solder joints with 100, 50, 20 and 10 μm SOH were prepared by the same reflow process and isothermally aged at 150°C. The IMC microstructural evolution was observed using scanning electron microscopy.

The whole IMC layer (Cu₃Sn + Cu₆Sn₅) grew faster in the solder joints with lower SOH because of the thinner IMC layer before aging. Also, the IMC proportion increased more rapidly in solder joints with the lower SOH. In all solder joints with different SOH, the growth rates of the Cu₃Sn (ϵ) layers were similar, and slowed down with increasing aging time. The Cu₆Sn₅ (η) was consumed by the Cu₃Sn (ϵ) growth at the beginning of the aging stage; while it turned to thickening after a period of aging. Finally, the Cu₆Sn₅ thickness was similar in all the solder joints. It is inferred that the thickness ratio of Cu₃Sn to Cu₆Sn₅ would maintain a dynamic balance in the subsequent aging. Based on the diffusion flux ratio of Cu to Sn at the ϵ/η interface, a model has been established to explain the microstructural evolution of IMC layers in high‐density solder interconnects with reduced SOH. In the model, interfacial reactions are mainly supposed to occur at the ϵ/η interface.

The findings provide electronic packaging reliability engineers with an insight into IMC microstructural evolution in high‐density solder interconnects with reduced SOH.

An innovative embedded chip MCM technology is being developed to address the packaging needs of the high volume, non‐military electronics industries. This development has evolved out of the GE High Density Interconnect (HDI) embedded chip MCM technology that was aimed at very high performance electronics in harsh military environments. In the HDI process, multiple bare chips are placed into cavities formed in a ceramic substrate and interconnected using an overlay polymer film, thin film metallisation and laser formed vias. Multiple levels of fine line (20 to 40 microns) interconnections and reference planes are used to form the circuit. In this new process, a plastic encapsulated substrate is formed by moulding a polymer resin around the bare die after placement on to a flat polymer film pre‐coated with an adhesive layer. After curing of the resin, the circuit is formed by patterning via holes through the polymer film to the components, metallising the polymer film and patterning the metal into the desired interconnect pattern. Feature sizes are readily scaled to the complexity needed by the circuit, permitting the use of lower cost and higher yield board photopatterning processes and equipment. This paper will cover the development of this low cost technology and will describe the process. It will also describe the thermal, mechanical and electrical features of this process and show actual working prototype modules.

CSP (chip scale packaging) and flip chip area array technologies are emerging within the electronics packaging industry to provide solutions capable of fulfilling the technological demands of computer, telecom and consumer electronic products. However, the full potential of area array attach can only be realised if the next level of interconnect is capable of supporting the fine pitch and high I/O characteristics of emerging CSP and flip chip technology. Celestica has addressed this issue by investigating next generation printed circuit board (PCB) technology, to assess the capability of organic based laminate as a high density interconnect. This paper describes the manufacturing experiments performed to produce a laser microvia interconnect solution. The mechanical performance of the interconnect is also presented to confirm its compatibility with area array assembly.

The purpose of this paper is to study the microstructure and mechanical behaviour of smaller microbumps for high density solder interconnects.

The microstructure was analyzed by scanning electron microscopy and electron backscatter diffraction tests to determine the Sn grain number of the resultant microbumps. The nanomechanical properties of Sn microbumps were investigated by the nanoindentation and shearing tests to understand the failure mechanism and assess the reliability of ultra-high density solder interconnects with numbered grains.

Only one Sn grain is observed in the interconnect matrix when the microbumps are miniaturized to 40 μm or less. Because of the body-centred tetragonal lattice of ß-Sn unit cell, the mechanical properties of the one-grain Sn microbumps are remarkably anisotropic, which are proved by the difference of the elastic modulus and the stiffness in the different orientations. The shearing tests show that the one-grain Sn microbump has a typical brittle sliding fracture of monocrystal at different shearing speeds.

The paper provides a comparable study for the performance of the bigger solder joints and also makes preliminary research on the microstructure and mechanical behaviour of Sn microbumps with the diameter of 40 μm.

The findings in this paper provide methods of microstructure study by combination of EBSD test and metallographic analysis, mechanical study by combination of nanoindentation test and shearing test, which can provide good guidelines for other smaller microbumps. The strain rate sensitivity exponent of the one-grain Sn microbumps is consistent with the Pb-free bulk solder. This implies that the one-grain Sn microbump has a comparable flow stress to Sn37Pb solder, which is beneficial for Pb-free replacement in higher density microelectronic packaging.

This paper looks at the implications of increases in system speed and density for the interconnection system, noting particularly the increased requirements placed on the substrate and tracking system. It reviews the properties required of substrates and the limitations derived from the materials used and the processes needed to put tracks on them. Those areas where these requirements are in conflict are highlighted, including such low technology problems as the limited size availability of substrate prepregs which may limit the tracking density achievable on the newer, more advanced low dielectric materials. Some limitations and trade‐offs are identified.

There has been increasing interest in the development of printable electronics to meet the growing demand for low‐cost, large‐area, miniaturized, flexible and lightweight devices. The purpose of this paper is to discuss the electronic applications of novel printable materials.

The paper addresses the utilization of polymer nanocomposites as it relates to printable and flexible technology for electronic packaging. Printable technology such as screen‐printing, ink‐jet printing, and microcontact printing provides a fully additive, non‐contacting deposition method that is suitable for flexible production.

A variety of printable nanomaterials for electronic packaging have been developed. This includes nanocapacitors and resistors as embedded passives, nanolaser materials, optical materials, etc. Materials can provide high‐capacitance densities, ranging from 5 to 25 nF/in², depending on composition, particle size, and film thickness. The electrical properties of capacitors fabricated from BaTiO₃‐epoxy nanocomposites showed a stable dielectric constant and low loss over a frequency range from 1 to 1,000 MHz. A variety of printable discrete resistors with different sheet resistances, ranging from ohm to Mohm, processed on large panels (19.5×24 inches) have been fabricated. Low‐resistivity materials, with volume resistivity in the range of 10⁻⁴‐10⁻⁶ ohm cm, depending on composition, particle size, and loading, can be used as conductive joints for high‐frequency and high‐density interconnect applications. Thermosetting polymers modified with ceramics or organics can produce low k and lower loss dielectrics. Reliability of the materials was ascertained by (Infrared; IR‐reflow), thermal cycling, pressure cooker test (PCT) and solder shock testing. The change in capacitance after 3× IR‐reflow and after 1,000 cycles of deep thermal cycling between −55°C and +125°C was within 5 per cent. Most of the materials in the test vehicle were stable after IR‐reflow, PCT, and solder shock.

The electronic applications of printable, high‐performance nanocomposite materials such as adhesives (both conductive and non‐conductive), interlayer dielectrics (low‐k, low‐loss dielectrics), embedded passives (capacitors and resistors), and circuits, etc.. are discussed. Also addressed are investigations of printable optically/magnetically active nanocomposite and polymeric materials for fabrication of devices such as inductors, embedded lasers, and optical interconnects.

A thin film printable technology was developed to manufacture large‐area microelectronics with embedded passives, Z‐interconnects and optical waveguides, etc. The overall approach lends itself to package miniaturization because multiple materials and devices can be printed in the same layer to increase functionality.

Emerging ‘chip‐size’ packages, and bare flip‐chips, require new substrate properties if high lead count chips are to be reliably interconnected on printed wiring boards and multichip modules at low cost. Blind via holes have been shown to increase interconnect density significantly without adding layers which contribute to high cost. Until recently, the use of blind vias has been limited to high‐end applications since standard fabrication methods, either sequential lamination or controlled depth drilling, are too slow and expensive for most high volume commercial applications. To maintain a low layer count while interconnecting higher I/O packages, commercial and consumer electronics require a substrate technology which supports high speed, micro‐via hole formation. This paper describes a process for fabricating high speed micro‐vias in dimensionally stable non‐woven Aramid reinforced laminates using laser ablation technology. Laser equipment capable of producing over 100 blind micro‐via holes per second is discussed. The process steps of hole cleaning and plating are reviewed, showing how existing PWB manufacturing technologies can be used. This process is compared with other methods of generating small holes and blind vias in printed wiring boards. In addition, requirements for flip‐chip and chip‐size packages, including a coefficient of thermal expansion of <10 ppm/°C and thin laminate dimensional stability of <0.03%, are explained.