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The purpose of this work in designing a wideband ring voltage-controlled oscillator (VCO) based on programmable current topology. It occupies a very tiny area yet achieving a good phase noise performance, which is suitable to be implemented in cost-effective and wideband frequency synthesizers.

The tuning range and gain are improved by dividing the VCO tuning curve into multiple curves controlled by programmable current sources without introducing additional parasitic capacitance.

Fabricated in 130-nm standard complementary metal oxide semiconductor technology and occupying an area of 0.079 mm², the VCO is tunable from 2.05 to 4.19 GHz, with a tuning percentage of 68.5 per cent. The VCO measures a phase noise performance of −96.7 dBc/Hz at an offset of 1 MHz from a 4.19 GHz carrier while consuming an average current of 6.5 mA, achieving figure of merit (FoM) and FoM_T of −158.9 and −175.6 dBc/Hz, respectively.

The proposed design uses programmable current topology without introducing parasitic capacitance, hence achieving wideband operation. It also occupies a tiny area and achieves a good phase noise performance.

This paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a WLAN transmitter application in 0.18‐μm deep submicron CMOS technology.

A folded current draining low‐voltage mixer architecture is explored and an extensive simulation carried out utilizing Cadence Spectre‐RF tool in optimizing the linearity, input third‐order intercept point (IIP3), the dynamic range, 1 dB compression point (P_−1dB), power dissipation and reduction of switching quad C_gs, input gate‐source capacitance, in enhancing the switching efficiency of the proposed architecture.

A highly linear, high input dynamic range, low voltage folded up‐conversion mixer architecture is realized in a significant comparable performance with respect to conventional reported architecture, indicating −8.87 dBm of OIP3 corresponding to 15.27 dBm IIP3 and 4.37 dBm of P_−1dB in 0.18‐μm CMOS technology.

The optimized mixer architecture is stringent to an up‐converter application. To be utilized as a down converter at the receiver end, parameters, namely as noise figure and conversion gain, are of additional importance.

The designed folded mixer architecture is in need of integration to a two‐step up‐conversion transmitter architecture which relaxes the injection pulling effect for a given low voltage headroom, with low power dissipation design.

In this work, an integrated folded architecture with on‐chip process, voltage and temperature compensated biasing circuit is explored and enhanced, raising awareness of adapting improved multiplier blocks in achieving optimal performance in WLAN transceiver architecture.

The purpose of this paper is to design and realize a high gain power amplifier (PA) with low output back-off power using the InGaP/GaAs HBT process for WCDMA applications from 1.85 to 1.91 GHz.

A three stages cascaded PA is designed which observes a high power gain. A 100 mA of quiescent current helps the PA to operate efficiently. The final stage device dimension has been selected diligently in order to deliver a high output power. The inter-stage match between the driver and main stage has been designed to provide maximum power transfer. The output matching network is constructed to deliver a high linear output power which meets the WCDMA adjacent channel leakage ratio (ACLR) requirement of −33 dBc close to the 1 dB gain compression point.

With the cascaded topology, a maximum 31.3 dB of gain is achieved at 1.9 GHz. S11 of less than −18 dB is achieved across the operating frequency band. The maximum output power is indicated to be 32.7 dBm. An ACLR of −33 dBc is achieved at maximum linear output power of 31 dBm.

The designed PA is an excellent candidate to be employed in the WCDMA transmitter chain without the aid of additional driver amplifier and linearization circuits.

In this work, a fully integrated GaAs HBT PA has been implemented which is capable to operate linearly close to its 1 dB gain compression point.

The purpose of this paper is to design and realize a low‐phase noise, high‐output power, and high‐tuning range, fully integrated source injection parallel coupled (SIPC)‐based inductor‐capacitor (LC)‐quadrature voltage controlled oscillator (QVCO) covering WiMAX frequency range in 0.18‐μm deep submicron CMOS technology.

A pMOS based‐SIPC LC‐QVCO topology is realized with the center frequency of 2.58 GHz. On chip spiral inductor is integrated with substantial quality factor, Q coupled with underlying pattern ground shield (PGS) shielding. An enhanced tuning range is achieved by integrating the diode connected MOS‐based varactors. The CMOS‐based autonomous SIPC LC‐QVCO circuit was characterized for its output phase noise, tuning range and power spectrum response via wafer probing, utilizing a signal source analyzer (Agilent E5052 A).

A quadrature oscillator catering to the needs of local oscillator (LO) generation covering the frequency range of WiMAX is realized. The parallel coupled architecture adapts direct source coupling, bypassing the LC resonator tank and relaxes the close in phase noise up‐conversion. The design consumes 2.19 mm² of active chip area and measures a phase noise of −114.34 dBc/Hz at 1 MHz of offset frequency with 2.67 GHz of output frequency at 0.9 V of input tuning voltage. The corresponding output power measures to be −10.1 dBm, well suited for mixer hard switching. The design is realized in one poly, six metal 0.18‐μm standard CMOS technology.

Owing to convergence discrepancy in the analysis, a diode‐connected MOS varactor is adapted in contrary to the accumulation mode MOS varactors with superior tuning range.

The designed SIPC LC‐QVCO is of need in the generation of low‐phase noise, highly matched quadrature LO generation covering the WiMAX frequency range. The adapted parallel coupling also relaxes the voltage headroom limitation.

This paper shows how a fully integrated CMOS‐based SIPC LC‐QVCO architecture is adapted with low‐output phase noise and low voltage headroom consumption covering the WiMAX frequency range.

As commercial and military aircraft continue to be subject to direct lightning flashes, there is a great need to characterize correctly the electrical currents and electric potential fluctuations on an aircraft to determine alternative design approaches to minimizing the severity of the lightning-aircraft dynamics. Moreover, with the increased severity of thunderstorms due to global warming, the need arises even more to predict and quantify electrical characteristics of the lightning-aircraft electrodynamics, which is normally not measurable, using a reliable electric model of the aircraft. Such a model is advanced here. The paper aims to discuss these issues.

The case considered in this paper is that of an aircraft directly attached to an earth flash lightning channel. The paper develops a new approach to modelling the aircraft using electric dipoles. The model has the power to represent sharp edges such as wings, tail ends and radome for any aircraft with different dimensions by using a number of different sized dipoles. The distributed transmission line model (TLM) of the lightning return stroke incorporating the distributed aircraft model is used to determine aircraft electrical elements and finally the electric current induced on the aircraft body due to lightning's interaction with the aircraft. The model is validated by the waveform method and experimental results.

The dipole model proposed is a very powerful tool for minute representation of the different shapes of aircraft frame and to determine the best geometrical shape and fuselage material to reduce electric stress. This charge simulation method costs less computer storage and faster computing time.

The paper for the first time presents a computer-based simulation tool that allows scientists and engineers to study the dynamics of voltage and current along the aircraft surface when the aircraft is attached to a cloud to ground lightning channel.