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Book part
Publication date: 16 September 2017

Kevin J. Boudreau

Rather than organize as traditional firms, many of today’s companies organize as platforms that sit at the nexus of multiple exchange and production relationships. This chapter…

Abstract

Rather than organize as traditional firms, many of today’s companies organize as platforms that sit at the nexus of multiple exchange and production relationships. This chapter considers a most basic question of organization in platform contexts: the choice of boundaries. Herein, I investigate how classical economic theories of firm boundaries apply to platform-based organization and empirically study how executives made boundary choices in response to changing market and technical challenges in the early mobile computing industry (the predecessor to today’s smartphones). Rather than a strict or unavoidable tradeoff between “openness-versus-control,” most successful platform owners chose their boundaries in a way to simultaneously open-up to outside developers while maintaining coordination across the entire system.

Details

Entrepreneurship, Innovation, and Platforms
Type: Book
ISBN: 978-1-78743-080-8

Keywords

Article
Publication date: 22 December 2023

Vaclav Snasel, Tran Khanh Dang, Josef Kueng and Lingping Kong

This paper aims to review in-memory computing (IMC) for machine learning (ML) applications from history, architectures and options aspects. In this review, the authors investigate…

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Abstract

Purpose

This paper aims to review in-memory computing (IMC) for machine learning (ML) applications from history, architectures and options aspects. In this review, the authors investigate different architectural aspects and collect and provide our comparative evaluations.

Design/methodology/approach

Collecting over 40 IMC papers related to hardware design and optimization techniques of recent years, then classify them into three optimization option categories: optimization through graphic processing unit (GPU), optimization through reduced precision and optimization through hardware accelerator. Then, the authors brief those techniques in aspects such as what kind of data set it applied, how it is designed and what is the contribution of this design.

Findings

ML algorithms are potent tools accommodated on IMC architecture. Although general-purpose hardware (central processing units and GPUs) can supply explicit solutions, their energy efficiencies have limitations because of their excessive flexibility support. On the other hand, hardware accelerators (field programmable gate arrays and application-specific integrated circuits) win on the energy efficiency aspect, but individual accelerator often adapts exclusively to ax single ML approach (family). From a long hardware evolution perspective, hardware/software collaboration heterogeneity design from hybrid platforms is an option for the researcher.

Originality/value

IMC’s optimization enables high-speed processing, increases performance and analyzes massive volumes of data in real-time. This work reviews IMC and its evolution. Then, the authors categorize three optimization paths for the IMC architecture to improve performance metrics.

Details

International Journal of Web Information Systems, vol. 20 no. 1
Type: Research Article
ISSN: 1744-0084

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Article
Publication date: 1 March 2021

Anil Kumar Uppugunduru and Syed Ershad Ahmed

Multipliers that form the basic building blocks in most of the error-resilient media processing applications are computationally intensive and power-hungry modules. Therefore…

Abstract

Purpose

Multipliers that form the basic building blocks in most of the error-resilient media processing applications are computationally intensive and power-hungry modules. Therefore, improving the multiplier’s performance in terms of area, critical path delay and power has become an important research area. This paper aims to propose two improved multiplier designs based on a new approximate compressor circuit to reduce the hardware complexity at the partial product reduction stage. The proposed approximate 4:2 compressor design significantly reduces the overall hardware cost of the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure.

Design/methodology/approach

The multiplier designs implemented using the proposed approximate 4:2 compressor are targeted for error-resilient applications. For fair comparisons, various multiplier designs, including the proposed one, are implemented in MATLAB. The quality analysis is carried out using standard images, and metrics such as structural similarity index are computed to quantify the result of proposed designs with the existing architectures. Next, Verilog gate-level designs are synthesized to compute area, delay and power to prove the efficacy of the proposed designs.

Findings

Exhaustive error and hardware analysis have been carried out for the existing and proposed multiplier architectures. Error analysis carried out using MATLAB proves that the proposed designs achieve better quality metrics than existing designs. Hardware results show that area, the power consumed and critical path delay are reduced up to 39.8%, 51.7% and 15.9%, respectively, compared to the existing designs. Toward the end, the proposed designs impact is quantified and compared with existing designs on real-time image sharpening and image multiplication applications.

Originality/value

The area, delay and power metrics of the multiplier can be improved using an approximate compressor in an error-resilient application. Accordingly, in this work, a new compressor is proposed that reduces the hardware complexity in the multiplier architecture. However, the proposed approximate compressor, while reducing the computational complexity, tends to introduce error in the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure. With the help of the approximate compressor and a technique of input realignment, hardware efficient and highly accurate multiplier designs are achieved.

Details

Circuit World, vol. 48 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 13 July 2010

S.P. Joy Vasantha Rani and K. Aruna Prabha

The purpose of this paper is to implement the hardware structure for radial basis function (RBF) neural network based on stochastic logic computation.

Abstract

Purpose

The purpose of this paper is to implement the hardware structure for radial basis function (RBF) neural network based on stochastic logic computation.

Design/methodology/approach

The hardware implementation of artificial neural networks (ANNs) has a complicated structure and is normally space consuming due to huge size of digital multiplication, addition/subtraction, non‐linear activation function, etc. Also the unavailability of ANN hardware at an attractive price limits its use for real time applications. In stochastic logic theory, the real numbers are converted to random streams of bits instead of a binary number. The performance of the proposed structure is analyzed using very high speed integrated circuit hardware description language.

Findings

Stochastic theory‐based arithmetic and logic approach provides a way to carry out complex computation with very simple hardware and very flexible design of the system. The Gaussian RBF for hidden layer neuron is employed using stochastic counter that reduces the hardware resources significantly. The number of hidden layer neurons in RBF neural network structure is adaptively varied to make it an intelligent system.

Originality/value

The paper outlines the stochastic neural computation on digital hardware for implementing radial basis neural network. The structure has considered the optimized usage of hardware resources.

Details

Journal of Engineering, Design and Technology, vol. 8 no. 2
Type: Research Article
ISSN: 1726-0531

Keywords

Open Access
Article
Publication date: 28 March 2022

Yunfei Li, Shengbo Eben Li, Xingheng Jia, Shulin Zeng and Yu Wang

The purpose of this paper is to reduce the difficulty of model predictive control (MPC) deployment on FPGA so that researchers can make better use of FPGA technology for academic…

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Abstract

Purpose

The purpose of this paper is to reduce the difficulty of model predictive control (MPC) deployment on FPGA so that researchers can make better use of FPGA technology for academic research.

Design/methodology/approach

In this paper, the MPC algorithm is written into FPGA by combining hardware with software. Experiments have verified this method.

Findings

This paper implements a ZYNQ-based design method, which could significantly reduce the difficulty of development. The comparison with the CPU solution results proves that FPGA has a significant acceleration effect on the solution of MPC through the method.

Research limitations implications

Due to the limitation of practical conditions, this paper cannot carry out a hardware-in-the-loop experiment for the time being, instead of an open-loop experiment.

Originality value

This paper proposes a new design method to deploy the MPC algorithm to the FPGA, reducing the development difficulty of the algorithm implementation on FPGA. It greatly facilitates researchers in the field of autonomous driving to carry out FPGA algorithm hardware acceleration research.

Details

Journal of Intelligent and Connected Vehicles, vol. 5 no. 2
Type: Research Article
ISSN: 2399-9802

Keywords

Article
Publication date: 7 April 2023

Ibrahim Ayaz, Ufuk Sakarya and Ibrahim Hokelek

The purpose of this paper is to present a verification methodology for custom micro coded components designed for Avionics projects. Every electronic hardware which will be…

Abstract

Purpose

The purpose of this paper is to present a verification methodology for custom micro coded components designed for Avionics projects. Every electronic hardware which will be developed for an aircraft must be designed with the compliance of DO-254 processes. Requirements are the key elements of the aviation. All the requirements must be covered by the design to be considered as completed. Therefore, verification of the custom micro coded components against requirements should be comprehensively addressed. The verification using the manual testing approach is less preferable, as humans can possibly make mistakes. Therefore, the most used verification method today is the automated simulation.

Design/methodology/approach

The industry has developed a common methodology for generating automated testbenches by following the standardized guideline. This methodology is named as the universal verification methodology (UVM). In this paper, the verification study of ARINC-429 data bus digital design is presented to describe the DO-254 verification process using the UVM.

Findings

The results are supported with functional coverage and code coverage in addition to the assertions. It is observed that the design worked correctly.

Originality/value

To the best of the authors’ knowledge, this is the first study comprehensively describing the DO-254 verification process and demonstrating it by the UVM application of ARINC-429 on programmable logic devices.

Details

Aircraft Engineering and Aerospace Technology, vol. 95 no. 7
Type: Research Article
ISSN: 1748-8842

Keywords

Article
Publication date: 1 March 1994

William J. Caelli

Distributed computing systems impose new requirements on the security ofthe operating systems and hardware structures of the computersparticipating in a distributed data network…

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Abstract

Distributed computing systems impose new requirements on the security of the operating systems and hardware structures of the computers participating in a distributed data network environment. It is proposed that multiple level (greater than two) security hardware, with associated full support for that hardware at the operating system level, is required to meet the needs of this emerging environment. The normal two layer (supervisor/user) structure may probably be insufficient to enforce and protect security functions consistently and reliably in a distributed environment. Such two‐layer designs are seen as part of earlier single computer/processor system structures while a minimum three/four‐layer security architecture appears necessary to meet the needs of the distributed computing environment. Such multi‐level hardware security architecture requirements are derived from earlier work in the area, particularly the Multics project of the mid‐1960s, as well as the design criteria for the DEC VAX 11/780 and Intel iAPX‐286 processor and its successors, as two later examples of machine structures. The security functions of individual nodes participating in a distributed computing environment, and their associated evaluation level, appear critical to the development of overall security architectures for the protection of distributed computing systems.

Details

Information Management & Computer Security, vol. 2 no. 1
Type: Research Article
ISSN: 0968-5227

Keywords

Article
Publication date: 20 June 2008

U. Hagn, M. Nickl, S. Jörg, G. Passig, T. Bahls, A. Nothhelfer, F. Hacker, L. Le‐Tien, A. Albu‐Schäffer, R. Konietschke, M. Grebenstein, R. Warpup, R. Haslinger, M. Frommberger and G. Hirzinger

Surgical robotics can be divided into two groups: specialized and versatile systems. Versatile systems can be used in different surgical applications, control architectures and…

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Abstract

Purpose

Surgical robotics can be divided into two groups: specialized and versatile systems. Versatile systems can be used in different surgical applications, control architectures and operating room set‐ups, but often still based on the adaptation of industrial robots. Space consumption, safety and adequacy of industrial robots in the unstructured and crowded environment of an operating room and in close human robot interaction are at least questionable. The purpose of this paper is to describe the DLR MIRO, a new versatile lightweight robot for surgical applications.

Design/methodology/approach

The design approach of the DLR MIRO robot focuses on compact, slim and lightweight design to assist the surgeon directly at the operating table without interference. Significantly reduced accelerated masses (total weight 10 kg) enhance the safety of the system during close interaction with patient and user. Additionally, MIRO integrates torque‐sensing capabilities to enable close interaction with human beings in unstructured environments.

Findings

A payload of 30 N, optimized kinematics and workspace for surgery enable a broad range of possible applications. Offering position, torque and impedance control on Cartesian and joint level, the robot can be integrated easily into telepresence (e.g. endoscopic surgery), autonomous or soft robotics applications, with one or multiple arms.

Originality/value

This paper considers lightweight and compact design as important design issues in robotic assistance systems for surgery.

Details

Industrial Robot: An International Journal, vol. 35 no. 4
Type: Research Article
ISSN: 0143-991X

Keywords

Article
Publication date: 15 January 2024

Arne Roar Nygård and Sokratis K. Katsikas

This paper aims to discuss the ethical aspects of hardware reverse engineering (HRE) and propose an ethical framework for HRE when used to mitigate cyber risks of the digital…

Abstract

Purpose

This paper aims to discuss the ethical aspects of hardware reverse engineering (HRE) and propose an ethical framework for HRE when used to mitigate cyber risks of the digital supply chain of critical infrastructure operators.

Design/methodology/approach

A thorough review and analysis of existing relevant literature was performed to establish the current state of knowledge in the field. Ethical frameworks proposed for other areas/disciplines and identified pertinent ethical principles have been used to inform the proposed framework’s development.

Findings

The proposed framework provides actionable guidance to security professionals engaged with such activities to support them in assessing whether an HRE project conforms to ethical principles. Recommendations on action needed to complement the framework are also proposed. According to the proposed framework, reverse engineering is neither unethical nor illegal if performed honourably. Collaboration with vendors and suppliers at an industry-wide level is critical for appropriately endorsing the proposed framework.

Originality/value

To the best of the authors’ knowledge, no ethical framework currently guides cybersecurity research, far less of cybersecurity vulnerability research and reverse engineering.

Details

Information & Computer Security, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 2056-4961

Keywords

Content available
Article
Publication date: 1 February 2002

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Abstract

Details

Aircraft Engineering and Aerospace Technology, vol. 74 no. 1
Type: Research Article
ISSN: 0002-2667

Keywords

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