Search results

1 – 10 of over 26000
Article
Publication date: 6 June 2016

Mayank Yuvaraj and Ambrish Kumar Maurya

This paper aims to introduce the concept of open-source hardware to the library professionals and gives a brief of the outlook of its current and potential application in libraries

Abstract

Purpose

This paper aims to introduce the concept of open-source hardware to the library professionals and gives a brief of the outlook of its current and potential application in libraries

Design/methodology/approach

The paper is based on a literature review.

Findings

Open source already aids libraries and has great potential but is hobbled by its intrinsically technical appeal.

Originality/value

The paper makes first observation towards the concept of open-source hardware with a slant towards librarianship.

Book part
Publication date: 16 September 2017

Kevin J. Boudreau

Rather than organize as traditional firms, many of today’s companies organize as platforms that sit at the nexus of multiple exchange and production relationships. This…

Abstract

Rather than organize as traditional firms, many of today’s companies organize as platforms that sit at the nexus of multiple exchange and production relationships. This chapter considers a most basic question of organization in platform contexts: the choice of boundaries. Herein, I investigate how classical economic theories of firm boundaries apply to platform-based organization and empirically study how executives made boundary choices in response to changing market and technical challenges in the early mobile computing industry (the predecessor to today’s smartphones). Rather than a strict or unavoidable tradeoff between “openness-versus-control,” most successful platform owners chose their boundaries in a way to simultaneously open-up to outside developers while maintaining coordination across the entire system.

Details

Entrepreneurship, Innovation, and Platforms
Type: Book
ISBN: 978-1-78743-080-8

Keywords

Book part
Publication date: 21 May 2010

Tim Kessler and Michael Stephan

As an answer for the limited growth potentials of diversification and internationalization, services became increasingly important for industrial firms in recent years…

Abstract

As an answer for the limited growth potentials of diversification and internationalization, services became increasingly important for industrial firms in recent years. Based on existing and established business concepts, companies explore new segments in their traditional value chains beyond traditional market penetration strategies: they pursue service transition strategies to open up new sources for growth, even in markets that do not promise great expansion potential. Our paper addresses the issue of economies of scope of service transition. In this context, we first explore the question, to what extent the insights about product diversification strategies from physical goods sectors can be transferred to the service sector. Using competence-based considerations on diversification we focus on dynamic economies of scope, whose central idea is exploration and development of new resources rather than the static exploitation of existing ones. Furthermore, we integrate the largely neglected issue of how the phenomenon of service diversification depends on the industry's life cycle stage. In a small empirical study of the German mechanical engineering industry we demonstrate that diversification steps into services require a shift in the resource and competence base of firms. Using a dynamic perspective, we construct a conceptual framework for analyzing and explaining the advantages of service transition strategies. The developed model describes a service diversification trajectory and points out that the establishment of a profitable service business requires the exploration and development of competences and adequate organizational structures.

Details

Enhancing Competences for Competitive Advantage
Type: Book
ISBN: 978-1-84855-877-9

Article
Publication date: 1 June 2000

George K. Chako

Briefly reviews previous literature by the author before presenting an original 12 step system integration protocol designed to ensure the success of companies or…

6159

Abstract

Briefly reviews previous literature by the author before presenting an original 12 step system integration protocol designed to ensure the success of companies or countries in their efforts to develop and market new products. Looks at the issues from different strategic levels such as corporate, international, military and economic. Presents 31 case studies, including the success of Japan in microchips to the failure of Xerox to sell its invention of the Alto personal computer 3 years before Apple: from the success in DNA and Superconductor research to the success of Sunbeam in inventing and marketing food processors: and from the daring invention and production of atomic energy for survival to the successes of sewing machine inventor Howe in co‐operating on patents to compete in markets. Includes 306 questions and answers in order to qualify concepts introduced.

Details

Asia Pacific Journal of Marketing and Logistics, vol. 12 no. 2/3
Type: Research Article
ISSN: 1355-5855

Keywords

Article
Publication date: 1 March 2013

Y.B. Liao, X. Han, Z.J. Zhu, Y. Wang and S. Kang

With the rapid development of integrated circuits, verification of SOC chips has become a great challenge due to its integration and complexity. Traditional software‐based…

Abstract

Purpose

With the rapid development of integrated circuits, verification of SOC chips has become a great challenge due to its integration and complexity. Traditional software‐based simulation methodology cannot meet verification needs. Therefore, FPGA‐based hardware acceleration technologies are requested in SOC verification. The classic methodology of hardware acceleration downloads the DUT (Device under Test) to the FPGA, while part of RTL codes and test bench is still run on the simulator in the workstation. Research found that the speed bottleneck of this methodology is mostly caused by the ping‐pong mode of data transmission between workstation software and the FPGA emulator, thus resulting in that channel transmission time takes too much proportion of total time. The purpose of this paper is to present a vector mode based hardware/software co‐emulation methodology, which leverages a pipeline structure to transmit, receive and buffer data. This methodology reduces the communication overhead by carrying out a parallel mechanism in that while user's design is under test in the emulator, signal data are transmitting in the channel simultaneously, thus increasing the speed of hardware acceleration and emulation.

Design/methodology/approach

The methodology of hardware acceleration proposed by this paper intercepts data for once from the emulation process of a traditional platform as test bench and utilizes direct memory access (DMA) channel to speed up data transfer, as well as increasing reasonable data caching mechanism, which reduces the ratio of channel transmission time in the entire emulation time, achieving accelerating emulation.

Findings

The proposed methodology and traditional hardware acceleration approach were tested on a quasi‐cyclic low‐density parity‐check (LDPC) decoder. Experiment results indicate that the proposed method can increase communication throughput 140 times compared with the traditional approach.

Originality/value

A vector mode based hardware/software co‐emulation methodology is presented in the paper. Higher communication throughput can be achieved by carrying out a parallel mechanism, as well as leveraging a pipeline structure to transmit, receive and buffer data.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 32 no. 2
Type: Research Article
ISSN: 0332-1649

Keywords

Article
Publication date: 1 May 2007

David J. Burns, David Duganne and E. Terry Deiderick

The purpose of this study is to compare the patrons of chain home centers and patrons of small hardware stores.

1015

Abstract

Purpose

The purpose of this study is to compare the patrons of chain home centers and patrons of small hardware stores.

Design/methodology/approach

A questionnaire was administered to individuals residing in two adjacent metropolitan areas located in the US Midwest. Respondents were contacted via telephone and were asked to respond to questions addressing their hardware store/home center preferences and shopping activity.

Findings

Respondents' assessments of the importance of eight attributes relating to shopping experience were not able to differentiate between patrons of small hardware stores and patrons of large home centers. Furthermore, the type of hardware retailer that individuals most commonly patronize does not appear to affect their assessments of various types of hardware retailers stores nor the amount of time respondents spent during a typical visit to their most patronized home center/hardware store. Finally, the only demographic difference noted involved income – respondents who shopped most often at large home centers were found to have a significantly higher income than those who shopped most often at small hardware stores.

Practical implications

The results of this study indicate that, at least for the issues examined, there appears to be relatively little difference between the individuals who patronize chain home centers and those who patronize small hardware stores. Consequently, individuals' choices of hardware retailer to patronize appears to be more complex than anticipated.

Originality/value

The growth of chains in hardware retailing has not received the same degree of attention as chain stores in other areas of retailing.

Details

International Journal of Retail & Distribution Management, vol. 35 no. 5
Type: Research Article
ISSN: 0959-0552

Keywords

Article
Publication date: 20 September 2022

Ashok Kumar L. and Kumaravel R.

The purpose of this paper is to check the Solar Photovoltaic (PV) inverter working condition with modified unipolar switching pulse. The gate pulse for the inverter…

Abstract

Purpose

The purpose of this paper is to check the Solar Photovoltaic (PV) inverter working condition with modified unipolar switching pulse. The gate pulse for the inverter switches is generated in MATLAB simulation and interfaced with hardware protype. Simulation results can be compared with hardware results.

Design/methodology/approach

A considerable amount of research has been done on different Pulse Width Modulation (PWM) techniques. Based on the findings, a modified Unipolar Sinusoidal PWM technique was created with one reference signal and two carrier signals+ (one for the positive half cycle and the other for the negative half cycle) and simulated in the MATLAB/Simulink platform. The prototype inverter module receives the simulated switching pulses via dSPACE DS1104 hardware software interfacing board. The hardware implementation has been done, and the hardware results compared with simulation results for various input voltage levels using resistive load.

Findings

This modified switching pulse has dead band and additional hardware setup is not required. 3-phase multi-level inverter output waveform has been achieved with six switches in this method and with low filter values, pure sine wave output can be obtained in simulation. By this method of switching pulse generation and testing, for every modification in switching pulse hardware gate driver is not required. Resulting time consumption and money investment are lower.

Originality/value

Modified Unipolar SPWM pulse generation technique is novel method for solar PV inverter. The switching pulse has been designed and tested in both MATLAB/Simulation and hardware prototype inverter. Hardware and software results are identical. This method of pulse generation and hardware implementation has not been done anywhere before.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 28 September 2007

Michael Georg Grasser

Embedded technologies are one of the fastest growing sectors in information technology today and they are still open fields with many business opportunities. Hardly any…

Abstract

Purpose

Embedded technologies are one of the fastest growing sectors in information technology today and they are still open fields with many business opportunities. Hardly any new product reaches the market without embedded systems components any more. However, the main technical challenges include the design and integration, as well as providing the necessary degree of security in an embedded system. This paper aims to focus on a new processor architecture introduced to face security issues.

Design/methodology/approach

In the short term, the main idea of this paper focuses on the implementation of a method for the improvement of code security through measurements in hardware that can be transparent to software developers. It was decided to develop a processor core extension that provides an improved capability against software vulnerabilities and improves the security of target systems passively. The architecture directly executes bound checking in hardware without performance loss, whereas checking in software would make any application intolerably slow.

Findings

Simulation results demonstrated that the proposed design offers a higher performance and security, when compared with other solutions. For the implementation of the Secure CPU, the SPARC V8‐based LEON 2 processor from Gaisler Research was used. The processor core was adapted and finally synthesised for a GR‐XC3S‐1500 board and extended.

Originality/value

As numerically, most systems run on dedicated hardware and not on high‐performance general purpose processors. There certainly exists a market even for new hardware to be used in real applications. Thus, the experience from the related project work can lead to valuable and marketable results for businesses and academics.

Details

International Journal of Web Information Systems, vol. 3 no. 1/2
Type: Research Article
ISSN: 1744-0084

Keywords

Article
Publication date: 13 July 2010

S.P. Joy Vasantha Rani and K. Aruna Prabha

The purpose of this paper is to implement the hardware structure for radial basis function (RBF) neural network based on stochastic logic computation.

Abstract

Purpose

The purpose of this paper is to implement the hardware structure for radial basis function (RBF) neural network based on stochastic logic computation.

Design/methodology/approach

The hardware implementation of artificial neural networks (ANNs) has a complicated structure and is normally space consuming due to huge size of digital multiplication, addition/subtraction, non‐linear activation function, etc. Also the unavailability of ANN hardware at an attractive price limits its use for real time applications. In stochastic logic theory, the real numbers are converted to random streams of bits instead of a binary number. The performance of the proposed structure is analyzed using very high speed integrated circuit hardware description language.

Findings

Stochastic theory‐based arithmetic and logic approach provides a way to carry out complex computation with very simple hardware and very flexible design of the system. The Gaussian RBF for hidden layer neuron is employed using stochastic counter that reduces the hardware resources significantly. The number of hidden layer neurons in RBF neural network structure is adaptively varied to make it an intelligent system.

Originality/value

The paper outlines the stochastic neural computation on digital hardware for implementing radial basis neural network. The structure has considered the optimized usage of hardware resources.

Details

Journal of Engineering, Design and Technology, vol. 8 no. 2
Type: Research Article
ISSN: 1726-0531

Keywords

Article
Publication date: 1 March 1993

Robert W. Stone and David J. Good

Examines the relationships between the frequency of expert systemuse and the system′s hardware, access location, and features. Alsoexamines the relationship between the…

Abstract

Examines the relationships between the frequency of expert system use and the system′s hardware, access location, and features. Also examines the relationship between the expert system′s hardware and access location. The study is empirical, using a survey of marketing executives who work within marketing organizations employing expert systems. The findings include that the hardware type appears to influence the frequency of expert systems use. Daily use is dominated by mainframe computers, while weekly and monthly use is dominated by the microcomputers. Further, the frequency of expert system use increases with access availability and decreases as the expert system becomes less available. The dominant feature of these expert systems is the ability to perform what‐if‐analysis. When access location and hardware type are examined, the dominant hardware is the microcomputer. Further, particular hardware types tend to dominate specific access locations.

Details

Industrial Management & Data Systems, vol. 93 no. 3
Type: Research Article
ISSN: 0263-5577

Keywords

1 – 10 of over 26000