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The subtractive method is widely used to produce high‐density PWBs. It is generally accepted that a pattern pitch of 100 microns or less cannot be achieved by the subtractive method because of the thickness of the copper layer to be etched. We report here on experiments to investigate the relationship between the pattern pitch of a circuit formed by the subtractive method and the required thickness of the copper layer. We have also determined the allowable thickness of the copper layer, plating layer, and copper foil layer for achieving a pattern pitch of 100 microns (L/S = 50/50 microns) or less.

While promising significant improvements in the cost and performance of electronic systems, the advent of new area array packaging concepts such as the BGA and newer area array CSPs has placed significant new demands on the substrates used in their interconnection. New methods such as build‐up multilayers and micro vias and co‐lamination of inner layers have been described and implemented by a number of different firms in an attempt to address this important issue. One such method employs simple double‐sided plated through hole flex circuits and the use of conductive pastes and bondplies to provide reliable electrical and mechanical connection between layers during a simple lamination cycle. The process, briefly described herein as a co‐laminated multilayer flex, is detailed in terms of both process steps and manufacturing flow. The structure of the interconnection substrate is also modeled and examined to determine its electrical performance potential according to electrical modeling software. Finally, detailed are the performance of the structure in reliability testing and an analysis of the expected design and performance advantages that might be obtained by such type constructions in combination with BGAs and area array CSPs.

In September 1998 six European companies involved in PCB manufacturing and electronic packaging started collaborating in a development project known as “PRIME”. The “Program for Re‐engineering and Innovating (PCB) Manufacturing and Equipment” project lost one of its original members in late 1999, and Coates Circuit Products joined as the dielectric supplier. The project is now approaching the mid‐term assessment (MTA), where alternative production scenarios will be discussed and the most attractive carried forward to fabricate test vehicles and ultimately demonstrator patterns. Some essential features of the project have already been demonstrated and these initial results will be presented.

This paper reveals a new methodology for predicting the most efficient design rules to follow for high density printed wiring boards prior to physical layout. The only input is from a schematic diagram, parts list and proposed board size. The methodology attempts to a priori determine the wiring capabilities of different PWB designs for a given product application. The particular focus is the difference between through‐hole and HDI designs.

For many years C‐MAC has used thick film technology in many electronic products for a large range of customer applications. A high degree of integration has been achievable, together with high reliability. Recently, however, new materials have been developed allowing for a further miniaturization. This paper reports on the development of a multilayer technology, based on the combination of state‐of‐the‐art Fodel^® materials with Diffusion Patterning™ dielectric and and standard thick film materials. The combination of such materials allows for the manufacture of high density products, addressing the present and future needs of many new applications. Besides the process technology for manufacturing the substrate, different assembly technologies like dip and reflow soldering and chip and wire bonding have been successfully investigated. In comparison to LTCC, this technology offers the possibility of using only a few layers, therefore allowing for faster product development, more flexibility during manufacturing and optimisation of cost.

Presents a survey of build‐up technologies based on the manufacture of microvia in thin dielectric sheets (< 100µm) deposited on PWB materials. These technologies will permit the PWB industry to manufacture high density interconnect substrates and answer the routeing requirements of high number I/Os, BGAs and new area array components. Bull Electronics Angers (BEA) has developed an HDI technology where microvias with hole diameters lower than 100µm are mechanically or laser drilled and interconnected lines at pitch down to 200µm are manufactured. In the frame of a European MEDEA project, ATEMAES, the design of an electronic subsystem manufactured by Magnetti Marelli in ceramic thick film technology has been adapted to the design rules of the HDI technology developed by Bull. This is part of an evaluation program for the use of HDI technology for automotive applications.

A developmental project has been initiated to create a new type of glass fabric, whose fibers are to be uniformly distributed in the laminate so as to comply with the requirement of homogeneity. As a result, various types of glass fiber fabrics have successfully woven through the uniquely developed “MS process”, and it has been verified that each of the glass fabrics possesses the most suitable structure to attain uniform distribution in the laminates. The laminates, using the newly developed glass fabrics, have proved that the micro‐diameter drilling, that is laser drilling and mechanical drilling with 0.1mm diameter, can be performed very easily with less drill bit breakage, and produces uniform drill holes. It has also been proved that the laminates with the new glass fabrics reveal improved mechanical properties such as lower CTE, decreased warp and twist and better dimensional stability compared with conventional laminates of glass epoxy. Various styles of new glass fabric cover the wide range of thickness from 100 microns down to 27 microns.