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Man has been seeking an ideal existence for a very long time. In this existence, justice, love, and peace are no longer words, but actual experiences. How ever, with the American preemptive invasion and occupation of Afghanistan and Iraq and the subsequent prisoner abuse, such an existence seems to be farther and farther away from reality. The purpose of this work is to stop this dangerous trend by promoting justice, love, and peace through a change of the paradigm that is inconsistent with justice, love, and peace. The strong paradigm that created the strong nation like the U.S. and the strong man like George W. Bush have been the culprit, rather than the contributor, of the above three universal ideals. Thus, rather than justice, love, and peace, the strong paradigm resulted in in justice, hatred, and violence. In order to remove these three and related evils, what the world needs in the beginning of the third millenium is the weak paradigm. Through the acceptance of the latter paradigm, the golden mean or middle paradigm can be formulated, which is a synergy of the weak and the strong paradigm. In order to understand properly the meaning of these paradigms, however, some digression appears necessary.

The use of Taguchi experimental design techniques to examine the effects of package type, solder paste type and solder reflow technique on the quality of fine pitch surface mount IC package solder joints is described. In particular, the effect of the use of ceramic or plastic packages, copper or Alloy 42 leadframes, silver loaded or non‐silver loaded solder paste and infra‐red, laser or hot‐bar reflow on solder joint metallurgical structure, electrical resistance and mechanical strength is evaluated. In addition to these solder joint parameters, an associated visual inspection was used to find the best process parameters to minimise solder balling, bridging etc. and a correlation between paste contacts at placement and solder bridges after reflow was also conducted. The experiment used an L9 array to find the optimum parameters from three factors, each at three levels. An extension to the basic Taguchi array was included in the form of an outer (noise) factor to include the effect of climatic stress on the solder joints under investigation. Response tables separate out the contribution of each factor level to the mechanical strength and electrical resistance of the assemblies. By comparing the response tables before and after climatic testing it is possible to estimate the effect of each factor level on the long‐term quality of the solder joints. It is shown how Taguchi experimental design techniques can be used to minimise the number of experiments required to predict optimum solder assembly process parameters. The accuracy of the prediction is shown by the results of a confirmation run which yielded mechanical strengths very close to those predicted, both before and after highly accelerated stress testing of the solder assemblies.

The purpose of this study is that the effects of surface mount technology (SMT) assembly process on the product lifetime of fine-pitch printed circuit boards (PCBs) were investigated under biased highly accelerated stress testing (HAST).

SMT assembly from a semiconductor SMT assembly process was replicated to test PCBs under the same conditions as SMT-assembled PCBs. The median lives µ and standard deviation s of the test PCBs were calculated from the log-normal distribution. The failure analysis of current leakages was conducted by the focused ion beam, scanning electron microscopy and energy-dispersive X-ray spectroscopy. Using the inverse power law and modified Peck-H’s relationship, the PCB lives at accelerated (by SMT assembly stress) and user conditions were calculated.

The failure analysis demonstrated that SiO₂ and BaSO₄ fillers added for stiffening organic materials promote current leakage failure. Therefore, the hydrophobicity of these fillers is believed to be necessary to suppress the current leakage failure under biased HAST. The inverse power law model indicates that the acceleration life model with SMT assembly stress can be given as follows: L(V) = 271.9(S)^−0.5031. From modified Peck-H’s relationship, after the third SMT assembly, the time required to attain 0.96 per cent failures at 35°C/60 per cent RH/1.9 V and 130°C/85 per cent RH/3.5 V are 129 y and 69.5 h, respectively. The biased HAST at 130°C/85 per cent/3.5 V after the third SMT assembly for 69.5 h on 238 samples could be recommended as an early quality-monitoring procedure.

In the future, the failure modes in an early stage of a bathtub should be analyzed and the life prediction model should be studied accordingly.

Through this study, the lifetime prediction model and early quality-monitoring procedure for organic substrates because of SMT assembly stress were obtained.

The purpose of this paper is to find optimal sintering conditions of silver-based nano-inks for achieving the high electrical conductivity of the deposited layers applied on polyimide foils as well as the influence of ageing on the electrical conductivity. Therefore, the investigation in the field of silver layers deposited by inkjet printing technology is presented in this paper.

The four-point resistance measurements were realized for a detailed and precise analysis of the resistance of two different silver layers under different sintering conditions depending on the type of nano-ink varied about the recommended values. Highly accelerated stress tests (HASTs) were also applied as an ageing method for confirmation of the high electrical stability of the silver layers.

The results prove the strong influence of the temperature and the time of the sintering process on the sheet resistance of the investigated silver-based layers deposited by inkjet printing technology on polyimide foils. The HASTs caused significant changes in the electrical conductivity for both nano-inks presented in this paper. The existence of noticeable dependence among the resistivity, thermal treatment and ageing was proved.

The main benefit lays in the optimization of sintering conditions to improve the electrical conductivity of the silver layers. The paper also presents a new approach for a stability analysis of the silver layers by HASTs.

KENT is one of the more beautiful of England's counties and one of the richest in ancient history. From the days of early invasions it has been in the forefront of national progress, habitation and culture; the number of family seats and landed gentry estates increased each decade, and by the eighteenth century Kent was among the premier parts chosen as a place of residence for the aristocracy, and those wishing to join that select circle. No contemporary history of that period was complete without reference to the families responsible for building the many lovely houses, landscaping the fallow countryside and populating the busy county towns.

The purpose of this paper is to compare the reliability and intermetallic layer (IML) of solder joints prepared with infrared (IR) and vapour phase (VP) soldering. The reliability of 0603-sized resistors’ solder joints formed with IR and VP soldering was investigated. The IML of the joints was analysed based on image processing algorithm automatically.

For the reliability analyses, the ageing method was a highly accelerated stress test (HAST) with +105°C maximum temperature, fully saturated (100 per cent) relative humidity at +0.5 atm overpressure. The joints were characterised based on the thickness of their IML and on their shear strength in as-reflowed stage, and after 400, 800, 1,200, 1,600 and 2,000 hours of HAST. An image processing algorithm was developed to measure the thickness of the IMLs on cross-sectional scanning electron microscopy (SEM) images automatically.

The increase of the IML thickness is lower in the case of HAST ageing compared to other methods. The thickness increment of the Cu₆Sn₅ layer was higher for IR and lower for VP soldering; the Cu₃Sn layer cannot be inspected even after 2,000 hours of HAST ageing. The results of shear strength measurements show better reliability for VP soldered joints.

The developed image processing method is applicable to obtain quantitative results about the IMLs in an effective fast way.

There is a lack of information in the literature regarding the reliability comparison of solder joints formed with VP and conventional reflow processes. Thus, we performed research about the lifetime of solder joints formed with VP and IR reflow method.

This paper will review the challenges brought by lead‐free soldering and some preliminary experimental evaluation results will be discussed. The initial results show that the lead‐free soldering process with 260°C reflow peak temperature does not directly cause failures for bismaleimide‐triazine (BT)‐based fine pitch ball grid array (FPBGA) packages. However, the strict lead‐free soldering condition could degrade the integrity of weak interface joints and potentially damage the package in subsequent unbiased highly accelerated stress test (unbiased HAST) evaluation. The impacts of lead‐free soldering with high reflow temperature on concurrent available electronics components could be more severe than previously believed. In the future, new materials and design concepts should be applied to enhance the package reliability under strict lead‐free soldering conditions.

This paper presents a study to determine the extent to which delamination at the die to encapsulant interface affects the package moisture content, and electrical failures when subjected to unbiased temperature‐humidity testing. Moisture absorption experiments showed that the presence of delamination did not significantly after the measurable moisture absorption characteristics of packages. Reliability testing indicated that although delamination is generally thought of as a reliability risk, it may not be a sufficient condition to promote damage in packages under dormant storage conditions. Experimental results showed no parametric or functional failures (or visible degradation) in packages with 100% die surface delamination after 1000 hours of unbiased testing at 140°C/85%RH.

Increasing board densities, decreasing spacing between holes and features and the growing requirement for printed circuit boards to perform in high temperature/high humidity environments have led to renewed concerns about possible reliability problems caused by the growth of Conductive Anodic Filaments (CAF). To date, there has been a lack of information on standardized test procedures and failure analysis methods for various types of prepregs and laminates.This paper introduces a standard test vehicle design and discusses suitable testing, failure analysis and board manufacturing methods. It also includes the requirements for CAF resistance and there is a discussion of material benchmarking tests with some preliminary results from this testing. These methods should be applicable to boards used in all market segments, including high density interconnect, and automotive applications.

The purpose of this paper is to provide a systematic review on technical findings and discuss the feasibility and future of gold (Au) wirebonding in microelectronics packaging. It also aims to study and compare the cost, quality and wear-out reliability performance of Au wirebonding with respect to other wire alloys such as copper (Cu) and silver (Ag) wirebonding. This paper discusses the influence of wire type on the long-term reliability tests.

Literature reviews are conducted based on cost and wire selections of Au, Cu or Ag wirebonding. Detailed wear-out failure findings and wire selection with cost considerations are presented in this review paper. The future and the status of Au wirebonding in microelectronics packaging are discussed in this paper.

This paper briefly reviews selected aspects of the Au ball and other alternative bonding options, focusing on reliability performance, and discusses the future of Au wirebonding in the near future in semiconductor packaging.

The paper reveals the technical considerations when choosing the wire types for future microelectronics packaging.

The in-depth technical review and strategies of the selection of wire types (Au, Cu or the latest Ag alloy) in microelectronics packaging are discussed in this paper based on previous literature studies.