Search results

This study empirically explores one of the important channel issues – the relationship between various channel support given to channel partners and the perceived (by managers) goal‐orientation of a firm. Results from an emerging market, India, indicate that perceived orientation towards both profitability and market share is not associated with any of the channel support considered. Growth orientation however is strongly associated with most of the channel support activities – both business (e.g., business advice, pricing and ordering assistance, and personnel training) as well as marketing (advertising support, sales promotional material, and inventory management assistance) oriented activities. In contrast, perceived sales volume orientation is only associated with advertising support and business advice, however, the relationship is negative. These findings have interesting implications for channel management and channel motivation.

The ageing behaviour of aluminium wire bonds (Al‐1%Si wire, 25 µm diameter) on five different gold thick film inks from three different manufacturers has been investigated. A new mechanism, the oxidation of the gold‐aluminium intermetallics, is proposed to explain the degradation of contact resistance for this system. With this theory the degradation of bond resistance, as well as the ‘healing effect’, can be explained. The oxidation can be proven by ageing in a vacuum. Surface analytical methods have shown the compound Au4Al to be responsible for the oxidation.

Aluminium nitride (AlN) is currently under investigation as a substrate material for use in microcircuit applications in particular where high thermal conductivity is required. Three commercially available substrate materials have been characterised using scanning electron microscopy (SEM), transmission electron microscopy (TEM) and X‐ray diffraction (XRD). The differences in thermal conductivity between the materials and also the difference from the theoretical thermal conductivity have been correlated to the presence of low thermal conductivity second phase regions between grains, defects within the crystal structure, the presence of oxygen impurities and poor sintering behaviour. The highest thermal conductivity substrate obtainable during this study was 140 W7m K. The substrates were identified as comprising hexagonal AIM having a wurtzite type structure. In addition, oxide and oxynitride phases were detected. The surface morphology of the substrates was also investigated, as it is the nature of the surface that will be of importance in determining the adhesion of applied films.

The compatibility of available AIN substrate materials with thin film metallisation processes is briefly discussed. The AIN material is shown to be covered with a very thin oxide layer. NiCr and NiCr‐Ni‐Au layers have been deposited onto the substrates; the adhesion between these layers and the ceramic is tested. In the substrate, via‐holes have been made by laser drilling, and the influences of the ambient gas atmosphere on the creation of such via‐holes have been observed. Advantages and limitations of the different methods of producing via‐holes that can be metallised are discussed. A high density hybrid circuit module on AIN is demonstrated.

An attempt is made to discuss the adhesion of thick film conductors on ceramic substrates in connection with thermally induced internal stresses caused by mismatch of the thermal expansion coefficient of the various layers and the substrate. The curvature of the bent substrates was taken as a measure of the internal stresses. A theoretical multilayer model is proposed for description of the composite — substrate/conductor/solder/intermetallic phases. This permits estimation of the stresses and the Young's modulus within the layers and explains the decrease of adhesion of the soldered copper layer after ageing.

Numerical techniques and experimental methods for the electrical characterisation and design of large multilayer thick film circuit boards are discussed. The numerical techniques investigated here include the boundary element and finite element methods for the estimation of capacitance and inductance and the method of normal modes for the analysis of voltage crosstalk between coupled transmission lines. Three‐dimensional capacitance and inductance calculations are included for typical thick film signal line and power and ground grid plane configurations. Numerical results are compared with measured data obtained from carefully constructed test coupons. Electrical characteristics of several popular high speed logic families and their compatibility with multilayer thick film interconnects are discussed and guidelines for the design of large thick film circuit boards for high speed digital applications are presented.

The challenge presented by advanced package development in the past five years has further accentuated the constant need for package quality and reliability monitoring through extensive laboratory testing and evaluation. As pin counts and chip geometries have continued to increase, there has been additional pressure from the military and commercial sectors to improve interconnect designs for packaged chips, including chips directly attached to the printed wiring board (PWB). One of the options employed has been tape automated bonding (TAB). However, this assembly technique also presents new standardisation, qualification and reliability problems. Therefore, at Rome Air Development Center (RADC), there is regular assessment (through in‐house failure analysis studies) of parts destined for military and space systems. In addition, Department of Defense (DoD) high tech development programmes, such as very high speed integrated circuits (VHSIC), have utilised all present screening methods for package evaluation, and have addressed the need for development of more definitive non‐destructive tests. To answer this need, two RADC contractual efforts were awarded on laser thermal and ultrasonic inspection techniques. Through these package evaluations, a number of potential reliability problems are identified and the results provided to the specific contractors for corrective action implementation. Typical problems uncovered are lid material and pin corrosion, damage to external components and adhesion problems between copper leads and polyimide supports, hermeticity failures, high moisture content in sealed packages and particle impact noise detection (PIND) test failures (internal particles). Further tests uncover bond strength failures, bond placement irregularities, voids in die attach material (potential heat dissipation problems), and die surface defects such as scratches and cracks. This presentation will review the specific package level physical test methods that are employed as a means of evaluating reliable package performance. Many of the tests, especially the environmental tests—e.g., salt atmosphere and moisture resistance—provide accelerated forms of anticipated conditions and are therefore applied as destructive tests to assess package quality and reliability in field use. In addition to a manufacturer's compliance with designated qualification procedures, the key to package quality lies in utilising good materials and well‐controlled assembly techniques. This practice, along with effective package screen tests, will ensure reliable operation of very large scale integration (VLSI) devices in severe military and commercial environment applications.

At present, over 95 percent of the manufactured packages are still being wire bonded. Owing to the ongoing trend of miniaturization, material changes, and cost reduction, wire bond‐related failures are becoming increasingly important. This paper aims to understand these kinds of failures.

Different finite element (FE) techniques are explored to their ability to describe the thermo‐mechanical behavior of the wire embedded in the electronic package. The developed nonlinear and parametric FE models are able to predict the strong nonlinear behavior of wire failures and multi‐failure mode interaction accurately and efficiently.

It is found that both processing and testing environments as well as the occurrence of delamination strongly increase the risk for wire failures. The results indicate that processing and testing influences are much less than those of the delamination.

Package designers should focus on limiting the occurrence of delamination around wire bond and/or stitch areas.

Combining the strengths of predictive modeling with simulation‐based optimization methods, the optimal wire shape is obtained.

The once highly publicised Porcelain Enamelled Steel (PES) substrates seem to have disappeared from the public gaze, or have they? They certainly have not. If anything, they have consolidated their place in electronics applications and are growing in use at a remarkable pace in particular applications supplied by the major USA source, namely Ferro‐ECA.