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Through the use of silicon‐on‐silicon packaging, VLSI chips can be interconnected by dense contacts and very fine conductor lines. Electrical and thermal properties obtained by means of this technique are discussed. The fabrication of small cooling channels in the silicon substrate and the application of the anodic bonding technique for chip mounting are demonstrated.

Tape automated bonding (TAB) is a suitable technology for assembling ICs with a high number of l/Os. The gang bonding process usually applied requires increasing thermode forces for chips with high lead counts and narrow tolerances regarding thermode parallelism and planarity. Due to the high bonding pressure, TC bonding of Au bumps to Au‐plated tapes becomes critical for these applications. In order to avoid damage to the pad structure an inner lead bonding (ILB) process with reduced pressure is required. A tape metallisation of 0.5–1.0 µm Sn is not sufficient for a significant reduction of thermode pressure. As an alternative, the application of an eutectic Au‐Sn cushion which is deposited on top of the bumps is presented. A modified bumping process was developed for the deposition of the solder bumps. Soldering of the Au‐Sn bumps to a Au‐plated tape was performed successfully by two techniques: thermode gang bonding and laser soldering. Bond parameters and tin layer thickness were optimised. Reliability investigations by thermal ageing were performed. The special metallurgical aspects of the system were investigated with a microprobe.

Tape Automated Bonding (TAB) is a modern technology which meets the requirements for micro‐connecting VLSI circuits. The limitations for gang bonding chips with high lead counts and reduced pitches are increased bond forces and induced mechanical stress. Laser soldering is an alternative for such contacts. Because microjoining of surfaces occurs via thermal energy from the laser beam, no mechanical pressure is necessary. Due to the optical properties of the laser beam and the possibility to reduce the laser spot, soldering of small pitches is possible. The results of TAB inner lead bonding with a pulsed Nd:YAG laser are presented. Tapes with three metallisations (Sn, Ni‐Sn and Au) were laser soldered to bumps consisting of gold and gold‐tin. The pull strength of laser soldered TAB‐contacts was optimised by variation of laser power and reliability investigations were performed. The metallurgy of laser soldering is different and more critical to long term reliability than that of gang bonded ILB‐contacts, even if identical tape and bump materials are applied. An accumulation of eutectic 80/20 Au‐Sn solder in the bonded interface results in a strong degradation due to Kirkendall pore formation in the ternary Cu‐Sn‐Au system. The application of a tape with a diffusion barrier of Ni inhibits this effect. But during thermal ageing these contacts show a strong degradation of pull forces which is attributed to the formation of brittle intermetallic compounds of the elements Ni, Sn and Au in the contact area. Laser soldering of Au‐plated tapes to Au‐Sn solder bumps is possible. The contacts show optimal pull forces and a minimal degradation after thermal ageing. This is attributed to the formation of an intermetallic compound with a high stability. The Zeta phase acts as a diffusion barrier between the copper lead and the eutectic Au‐Sn solder.

The development of high density packaging technologies offers cost reduction, smaller system volumes and better performance. High performance PCBs with fine line technology reach conductor widths of <0.1 mm and pitches of <0.2 mm. The limiting factors for higher densities of PCBs are the mechanically drilled through‐holes. In particular, the assembly of modern ICs with a pitch of less than 0.2 mm requires fine line technology and a simultaneous reduction of via diameters to minimise fan‐out areas. To meet these requirements, an interconnection system with photosensitive polyimide as an interdielectric thin film layer on top of a PCB is investigated. To demonstrate process feasibility, a test module including a test structure for measurement of contact resistance has been fabricated.

Multichip module packaging enables a significant increase of interconnect densities and performance of electronic systems. Multichip module technology based on laminate materials (MCM‐L) is attractive due to low cost and use of the standard equipment used by PCB manufacturers. The most limiting factor for higher wiring densities in PCB technology is the mechanical drilling of plated‐through holes. Using 0.3 mm drill diameters, 0.5 mm land diameters are required, which limit the area for routing of tracks. Therefore, alternative dielectric materials, which can be structured photolithograpically, by plasma etching or laser drilling, are very attractive for MCM‐L technology. In this paper an epoxy resin layer, commercially available as a solder mask, is investigated as an interdielectric layer. Via hole drilling is investigated using an excimer laser. To show process feasibility, a two‐layer wiring system is fabricated using the excimer laser structured epoxy resin as an interdielectric layer on conventional epoxy board (FR‐4).

Due to increasing density and high demands on electrical and thermal performance, modern packages require alternative chip interconnection and substrate technologies. Flip‐chip (FC) bonding is a suitable method for high interconnection densities. Compared with wire bonding and TAB, FC provides the highest contact density. This is due to the possibility of using the whole chip surface for bondpads (area bumps). In this paper, an adapted FC technology on green tape ceramic substrates was investigated. In order to reduce the substrate costs, FC bonding was performed directly on the thick film metallisation without the application of thin film technology for the upper substrate layers. Two solder bump metallurgies: PbSn95/5 and Au/Sn solder bumps were applied for fluxless FC bonding on adapted substrate metallisations. Fluxless soldering is performed by single chip bonding and requires substrates with narrow planarity tolerances. An alternative method using a wet eutectic Au/Sn solder paste on the substrate and Au bumps permits the application of substrates with standard planarity tolerances used in thick film applications. A common reflow of all chips of a multichip module is possible. First reliability results of metallurgical analysis and of the mechanical and electrical behaviour of the FC contacts after thermal cycling are presented.

Ball‐bumping is a flexible low cost bumping technology based on the conventional wire bonding procedure. It is applicable to single chips or whole wafers as well as to substrates. As established wire‐bonding machines can be used, expensive bumping‐process equipment for phototooling and plating is not necessary. Flip‐chip bonding is the most advantageous attach method of high frequency applications. Compared with wire‐bonding and TAB it allows the highest contact density, the shortest signal paths and lowest interconnection parasitics. The reduced pad sizes and pitches, not only of GaAs devices, demand a well controlled bump deformation during flip‐chip bonding. This work develops process parameters for the flip‐chip bonding of silicon and GaAs devices with respect to the best interconnection result by lowest bonding force and ball‐bump deformation. Ball‐bumps with diameters of 50 and 80 urn (2.0 and 3.2 mils) were created using 98% AuPd bump wire with diameters of 18 µm (0.7 mil) and 25 µm (1.0 mil) respectively. Ball‐bumping with a minimal pitch of 70 µm (2.8 mils) has been achieved. A special preparation allowed the shear test investigation of each bump/pad interface after flip‐chip attach. Bonding forces of 20 and 25 cN/bump respectively lead to a good welding in the bump/substrate interface due to the special shape of ball‐bumps. For silicon devices which have a pad metallisation of aluminium, the shear forces of the bump/pad interface increase after flip‐chip bonding, too. No cratering of GaAs and silicon occurs after flip‐chip bonding due to a low bonding force ramp of 5 cN/s and 10 cN/s respectively. The flip‐chip attach of a Fujitsu FLR 016 GaAs‐FET which has pad sizes of 35 urn is demonstrated. In this case, substrate bumping is the more advantageous bumping method. The feasibility of fine‐pitch TAB attach using ball‐bumps is introduced. 100 µm (3.9 mils) pitch silicon devices with 328 pads were ball‐bumped for both solder and thermal‐compression TAB. Bond forces were in the range of 9–11 cN/bump and 15–21 cN/bump respectively. Pull forces of approximately 30 cN/lead show good results of the bump/lead interconnection after TAB.

High performance aluminium nitride water cooled heat sinks were fabricated and characterized. A variety of fabrication processes were employed to meet different cooling requirements. They include laser cut microchannel coolers for chip and multichip heat sinks as well as dry pressed pin fin heat sinks for power electronics. Thermal simulation was used to optimize the heat sink design.

The advances in miniaturisation and ever increasing complexity of integrated circuits frequently mean an increase in the number of connections to a component with simultaneous reduction in pitch. For these emerging smaller contact geometries, micro‐laser connection technologies are required. The reliability of the connection plays a decisive rôle. The implementation and reproducibility of laser connections technology in micro‐electronics depend on good thermal contact between the two parts and high quality absorption of the material surface used. Laser energy can cause local melting due to overheating of the lead because of the low distance between lead and bump. This effect influences the reproducibility of the contacts. Even the slightest interruption in the thermal contact of the parts can cause non‐reproducibility of the contacts. Materials with a higher quality of absorption, for example Sn(32% ), can be soldered with a good level of reproducibility. This clearly differs from gold (4% ) or copper(7% ) surfaces. Due to the low absorption of these materials it is necessary to use a laser with a higher intensity to produce the same energy. Irregularities in the quality of absorption, laser instability and thermal contact can not guarantee reproducibility of the interconnections with this high laser intensity. The FPC (fibre push connection) system offers several solutions to the problems mentioned. This system enables the laser to be transported by fibre to the contact parts. The end piece of the fibre serves at the same time as a pushing unit. The advantage of this system is that the attenuation heat of the fibre end surface is also available for the connection. This improves the use of laser energy. As part of the laser energy at the end surface of the fibre is transformed into thermal energy, independently of the absorption quality of the material used, connection of a gold‐plated contact part is possible. By pressing the connecting parts with the tip of the fibre, optimal coupling is achieved. The reproducibility of different metallisations and the reliability of connections with a pitch below 100 μm are presented as well as further applications of this system.

During the last few years an increasing number of flip‐chip (FC) interconnection technologies have emerged. While flip‐chip assembly offers many advantages compared with conventional packaging techniques, several aspects prevent this technology from entering the high volume market. Among these are the availability of bumped chips and the costs of the substrates, i.e., ceramic substrates with closely matching coefficient of thermal expansion (CTE) to the chip, in order to maintain high reliability. Only recently, with the possibility of filling the gap between chip and organic substrate with an encapsulant, was the reliability of flip‐chips mounted on organic substrates significantly enhanced. This paper presents two approaches to a fluxless process, one based on soldering techniques using Au‐Sn metallurgy and the other on adhesive joining techniques. Soldering is performed with a thermode and with a laser based system. For both of these FC‐joining processes, alternative bump mettallurgies based on electroplated gold, electroplated gold‐tin, mechanical gold and electroless nickel gold bumps are applied.