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This paper aims to propose an efficient model for analysis of power electronic circuits with integrated magnetic components.

The inductance modeling technique is used as the traditional method for analyzing magnetic components. This model is simple and enough to generate for individual components, that is, an inductor and a transformer. However, it becomes difficult to realize this model for the integrated magnetic structures. This paper shows an appropriate model for individual magnetic components as well as integrated magnetic components and its application to magnetically coupled DC–DC converters. Gyrator–capacitor (G–C) modeling offers a unified, reasonable way of understanding the magnetic components commonly met with in power electronics and the other disciplines.

G–C model allows any electrical and magnetic circuit to be simultaneously simulated with circuit simulators. In this regard, this paper gives a complete simulation model and analysis as an illustrative example. There is no limitation of this paper or future works. The proposed G–C model can be applied to all power electronic circuits having integrated magnetic components.

In the proposed model, the magnetic circuit is converted to a pure electric circuit with capacitors and controlled sources; every winding is replaced with a pair of current controlled voltage sources, namely, a gyrator.

The paper presents a method of creating electrical equivalent diagrams of magnetic circuits. The method is based on bond‐graph techniques, using flux derivative as flow variable. Couplings between magnetic and electric part of the system are represented by gyrators. Simple models of magnetic branches, including non‐linear effects due to saturation, hysteresis and eddy currents, are presented. These models can be easily combined into magnetic circuit models, which can be transformed into dual electric equivalent circuit. Various equivalent circuits of transformers are discussed. The proposed models are simple and particularly useful for system‐level simulation of power electronic and motion control systems with magnetic elements. These models can be easily developed if needed. Theoretical considerations are illustrated by examples of digital simulation and experimental results.

The purpose of this research paper is to explore the possibility to enhance the power transfer from piezoelectric energy harvester (PEH) source to the load. As the proposed gyrator-induced voltage flip technique (GIVFT) does not require bulky components such as physical inductors, it is easily realizable in small integrated circuits (IC) package thereby offering performance benefits, reducing area overhead and providing cost benefits for constrained self-powered autonomous Internet-of-Things (IoT) applications.

This paper presents an inductorless interface circuit for PEH. The proposed technique is called GIVFT and is demonstrated using active elements. The authors use gyrator to induce voltage flip at the output side of PEH to enhance the charge extraction from PEH. The proposed technique uses the current-voltage (I-V) relationship of gyrator to get appropriate phasor response necessary to induce the voltage flip at the output of PEH to gain power transfer enhancement at the load.

The experimental results show the efficacy of the GIVFT realization for enhanced power extraction. The authors have compared their proposed design with popular earlier reported interface circuits. Experimentally measured performance improvement is 1.86×higher than the baseline comparison of full-wave bridge rectifier circuit. The authors demonstrated a voltage flip using GIVFT to gain power transfer improvement in piezoelectric energy harvesting.

To the best of the authors’ knowledge, pertaining to the field of PEH, this is the first reported GIVFT based on the I-V relationship of the gyrator. The proposed approach could be useful for constrained self-powered autonomous IoT applications, and it could be of importance in guiding the design of new interface circuits for PEH.

The purpose of this paper is to investigate the applicability of a direct current (DC) hysteresis measurement on power transformer terminals for the subsequent hysteresis model parametrization in transformer grey box topology models.

Two transformer topology models with two different hysteresis models are used together with a DC hysteresis measurement via the power transformer terminals to parameterize the hysteresis models by means of an optimization. The calculated current waveform with the derived model in the transformer no-load condition is compared to the measured no-load current waveforms to validate the model.

The proposed DC hysteresis measurement via the power transformer terminals is suitable to parametrize two hysteresis models implemented in transformer topology models to calculate the no-load current waveforms.

Different approaches for the measurement and utilization of transformer terminal measurements for the hysteresis model parametrization are discussed in literature. The transformer topology models, derived with the presented approach, are able to reproduce the transformer no-load current waveform with acceptable accuracy.

An annual substation equipment failure report says 3/7 capacitive voltage transformer (CVT) got damaged because of ferroresonance overvoltage. The conventional mitigation circuit fails to protect the transformer as the overvoltage may fall in the range between 2 and 4 per unit. It is necessary to develop a device to suppress the overvoltage as well as overcurrent of the CVT. This study aims to propose the suitability of memristor emulator as a mitigation circuit for ferroresonance.

The literature implies that a nonlinear circuit can protect the transformer against ferroresonance. An attempt is made with a memristor emulator using Operational Amplifier (OPAMP) for the mitigation of ferroresonance in a prototype transformer. The circuit is simulated using PSpice and validated for its ideal characteristics using hardware implementation. The nonlinear memductance is designed which is required to mitigate the ferroresonance. The mitigation performance has been compared with conventional method along with fast Fourier transform (FFT) analysis.

While the linear resistor recovers the secondary voltage by 74.1%, the memristor emulator does it by 82.05% during ferroresonance. Also, the total harmonic distortion (THD) of ferroresonance signal found to be 22.06% got improved as 2.56% using memristor emulator.

The suitability of memristor emulator as a mitigation circuit for ferroresonance is proposed in this paper. As ferroresonance occurs in instrument transformers which have extra high voltage (EHV) rated primary windings and (110 V/[110 V/1.732]) rated secondary windings, the mitigation device is proposed to be connected as a nonlinear load across the secondary windings of the transformer. This paper discusses the preliminary work of ferroresonance mitigation in a prototype transformer. The mitigation circuit may have memristor or meminductor for ferroresonance mitigation when they are commercially available in future.

The electronic component-based memristor emulator may not work at 110 V practically as they may be rated at low power. Hence, chemical component-based memristor emulator was developed to do the same. The authors like to clarify that the memristor will be a solution for ferroresonance in future not the memristor emulator circuit.

With the real form of memristor, the transistor world will be replaced by it and may have a revolution in the field of electronics, VLSI, etc. This contribution attempts to project the use of memristor in a smaller scale in high-voltage engineering.

The electronic component-based memristor emulator is proposed as a mitigation circuit for ferroresonance. The hypothesis has been verified successfully in a prototype transformer. Testing circuit of memristor emulator involves transformer, practically. The mitigation performance has been compared with conventional method technically and justified with FFT analysis.