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Article
Publication date: 3 August 2015

Piotr Markowski, Eugeniusz Prociów and Łukasz Urbaniak

The purpose of this paper is to determine the thermoelectric properties of the germanium-based thin films and selecting the most suitable ones for fabrication of…

Abstract

Purpose

The purpose of this paper is to determine the thermoelectric properties of the germanium-based thin films and selecting the most suitable ones for fabrication of micrognerators.

Design/methodology/approach

The germanium layers were deposited by low pressure magnetron sputtering method, in the pressure of 10−3/104 mbar range. The amount of dopants (germanium or vanadium) was changed in a limited extent. The influence of such changes on the layers output properties was studied. Post-processing heat treatment at temperature below 823 K was applied to activate the layers. It leads to improve the electrical and thermoelectrical performance.

Findings

The special attention was paid to the power factor (PF = S2/ρ) of the layers. To estimate power factor (PF) electrical resistivity (ρ) and Seebeck coefficient (S) were determined. The achieved Seebeck coefficient value was 185 Volt/Kelvin (μV/K) for germanium doped with vanadium (Ge:V1.15) and 225 μV/K for germanium doped with gold(Ge:Au3.13) layers at room temperature. After activation process, the PF reached a value of 2.5 × 10−4 W/m · K2 for the Ge:Au3.13 and 1.1 × 10−4 W/m · K2 for the Ge:V1.15 layers.

Originality/value

The fabricated thermoelectric layers can be thermally annealed in temperature up to 823 K in the air and in 1,023 K under a nitrogen atmosphere. This enables integration of thin layers with thick-film technology. Corning glass or low temperature cofired ceramic was used as a substrate.

Details

Microelectronics International, vol. 32 no. 3
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 28 October 2014

Abderrazzak El Boukili

The purpose of this paper is to provide a new three dimension physically based model to calculate the initial stress in silicon germanium (SiGe) film due to thermal…

Abstract

Purpose

The purpose of this paper is to provide a new three dimension physically based model to calculate the initial stress in silicon germanium (SiGe) film due to thermal mismatch after deposition. We should note that there are many other sources of initial stress in SiGe films or in the substrate. Here, the author is focussing only on how to model the initial stress arising from thermal mismatch in SiGe film. The author uses this initial stress to calculate numerically the resulting extrinsic stress distribution in a nanoscale PMOS transistor. This extrinsic stress is used by industrials and manufacturers as Intel or IBM to boost the performances of the nanoscale PMOS and NMOS transistors. It is now admitted that compressive stress enhances the mobility of holes and tensile stress enhances the mobility of electrons in the channel.

Design/methodology/approach

During thermal processing, thin film materials like polysilicon, silicon nitride, silicon dioxide, or SiGe expand or contract at different rates compared to the silicon substrate according to their thermal expansion coefficients. The author defines the thermal expansion coefficient as the rate of change of strain with respect to temperature.

Findings

Several numerical experiments have been used for different temperatures ranging from 30 to 1,000°C. These experiments did show that the temperature affects strongly the extrinsic stress in the channel of a 45 nm PMOS transistor. On the other hand, the author has compared the extrinsic stress due to lattice mismatch with the extrinsic stress due to thermal mismatch. The author found that these two types of stress have the same order (see the numerical results on Figures 4 and 12). And, these are great findings for semiconductor industry.

Practical implications

Front-end process induced extrinsic stress is used by manufacturers of nanoscale transistors as the new scaling vector for the 90 nm node technology and below. The extrinsic stress has the advantage of improving the performances of PMOSFETs and NMOSFETs transistors by enhancing mobility. This mobility enhancement fundamentally results from alteration of electronic band structure of silicon due to extrinsic stress. Then, the results are of great importance to manufacturers and industrials. The evidence is that these results show that the extrinsic stress in the channel depends also on the thermal mismatch between materials and not only on the material mismatch.

Originality/value

The model the author is proposing to calculate the initial stress due to thermal mismatch is novel and original. The author validated the values of the initial stress with those obtained by experiments in Al-Bayati et al. (2005). Using the uniaxial stress generation technique of Intel (see Figure 2). Al-Bayati et al. (2005) found experimentally that for 17 percent germanium concentration, a compressive initial stress of 1.4 GPa is generated inside the SiGe layer.

Details

COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, vol. 33 no. 6
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 1 July 1982

D. Barišin and C. Jelačič

Summary It has been noticed that during electrolysis of zinc from sulphate solutions in the presence of Germanium, the utilisation of current varies with the change of…

Abstract

Summary It has been noticed that during electrolysis of zinc from sulphate solutions in the presence of Germanium, the utilisation of current varies with the change of concentration of Ge in the electrolyte, and from the neutral electrolyte it decreases with the increase of current which passed through the electrolyte. Therefore dependencies of current utilisation on concentration of acid and concentration of Ge in the electrolyte have been investigated. It has been found the current utilisation decreases when the acidity increases, the decrease being also proportional to the increase of concentration of Ge. The activity of Ge is the more intensive with the higher the acidity. The cause of the fact that concentration of Ge in the electrolyte remains constant after a certain duration of electrolysis has been explained, as well as that the absolute value of this concentration depends only on the initial concentration of Ge. It has been stated that deposition of Ge on the cathode ceases (either in the form of metal or hydride) when the electrolyte has reached an acidity value of about 120 g/l H2SO4.

Details

Anti-Corrosion Methods and Materials, vol. 29 no. 7
Type: Research Article
ISSN: 0003-5599

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Article
Publication date: 1 October 2018

Arkadiy Skvortsov, Nikolay A. Khripach, Boris A. Papkin and Danila E. Pshonkin

This study aims to examine the electromigration processes resulting from thermal overloads of semiconductor devices. While in operation, parts of such devices can heat up…

Abstract

Purpose

This study aims to examine the electromigration processes resulting from thermal overloads of semiconductor devices. While in operation, parts of such devices can heat up to 330°C for a short period, resulting in the emergence of molten zones and the devices’ inevitable degradation. Therefore, this study examines the mechanisms behind the formation and migration of silver-based molten zones in bulk germanium and on its surface.

Design/methodology/approach

Experimental data concerning the correlation between the migration velocities of the inclusions and their sizes are obtained.

Findings

By comparing these experimental data with known electromigration models, it is concluded that inclusions move through the mechanism of melting and crystallization. The dynamics of Ge–Ag zones in the volume of a germanium crystal are compared to those on its surface and accelerated electromigration on the surface of the crystal is observed. This increased migration velocity is shown to be associated with additional contributions of the electrocapillary component.

Originality/value

The results of this study can be used to calculate the operating modes of semiconductor power devices under intense heat loading.

Details

Microelectronics International, vol. 35 no. 4
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 1 August 1968

Cyril Hogarth

Modern semiconductor physics has developed from the quantum mechanical work on energy band theory of charge carriers in semiconductors associated with the name of A. H…

Abstract

Modern semiconductor physics has developed from the quantum mechanical work on energy band theory of charge carriers in semiconductors associated with the name of A. H. Wilson and his classic papers on the subject, and also with the name of Schottky who pioneered the atomistic approach to disorder phenomena in solids. This work dates from about 1930 and theoretical developments up to the beginning of the War were relatively slow. Semiconductor technology in the same period was represented by a few devices only. These included the copper oxide and selenium rectifiers which were in use in certain equipment and in the process of further development. The silicon whisker detector was being used for the detection and measurement of microwave power. It will be recalled that silicon carbide and galena had been used as detectors of radio waves before the common usage of the thermionic valve. The development of radar during the War, which required semiconductor devices for detecting and mixing microwaves meant that considerable work was carried out on silicon, and parallel work on germanium meant that by the end of the War high‐back voltage rectifiers, using germanium, were available in developmental quantities. Problems of thermal detection meant that photo‐conductive and photo‐voltaic cells were developed for this purpose based on the materials thallium sulphide and lead sulphide. Attention was also focussed on electronic processes in ionic crystals in terms of improving display screens for cathode ray and similar tubes.

Details

Education + Training, vol. 10 no. 8
Type: Research Article
ISSN: 0040-0912

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Article
Publication date: 3 January 2017

Abderrazzak El Boukili

The purpose of this paper is to develop and apply accurate and original models to understand and analyze the effects of the fabrication temperatures on thermal-induced…

Abstract

Purpose

The purpose of this paper is to develop and apply accurate and original models to understand and analyze the effects of the fabrication temperatures on thermal-induced stress and speed performance of nano positively doped metal oxide semiconductor (pMOS) transistors.

Design/methodology/approach

The speed performances of nano pMOS transistors depend strongly on the mobility of holes, which itself depends on the thermal-induced extrinsic stress σ. The author uses a finite volume method to solve the proposed system of partial differential equations needed to calculate the thermal-induced stress σ accurately.

Findings

The thermal extrinsic stress σ depends strongly on the thermal intrinsic stress σ0, thermal intrinsic strain ε0, elastic constants C11 and C12 and the fabrication temperatures. In literature, the effects of fabrication temperatures on C11 and C12 needed to calculate thermal-induced stress σ0 have been ignored. The new finding is that if the effects of fabrication temperatures on C11 and C12 are ignored, then, the values of stress σ0 and σ will be overestimated and, then, not accurate. Another important finding is that the speed performance of nano pMOS transistors will increase if the fabrication temperature of silicon-germanium films used as stressors is increased.

Practical implications

To predict correctly the thermal-induced stress and speed performance of nano pMOS transistors, the effects of fabrication temperatures on the elastic constants required to calculate the thermal-induced intrinsic stress σ0 should be taken into account.

Originality/value

There are three levels of originalities. The author considers the effects of the fabrication temperatures on extrinsic stress σ, intrinsic stress σ0 and elastic constants C11 and C12.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 36 no. 1
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 1 March 1991

F. Kieffer and H. Schneider

There is a general notion that immunology represents one of the more recently emerged branches in the field of science. Its actual roots, however, go back to the late 19th…

Abstract

There is a general notion that immunology represents one of the more recently emerged branches in the field of science. Its actual roots, however, go back to the late 19th century when scientists like Louis Pasteur, Robert Koch and Paul Ehrlich — just to name a few — laid the basis for active immunisation against bacterial infections. Following the discovery of the virus and its structure, immunisation against viral infections was developed, the most spectacular and effective treatments being vaccinations against smallpox and poliomyelitis.

Details

Nutrition & Food Science, vol. 91 no. 3
Type: Research Article
ISSN: 0034-6659

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Article
Publication date: 25 February 2021

Sudipta Ghosh, P. Venkateswaran and Subir Kumar Sarkar

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads…

Abstract

Purpose

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Design/methodology/approach

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

Findings

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Originality/value

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

Keywords

Abstract

Details

Microelectronics International, vol. 22 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

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Article
Publication date: 1 October 1960

A.J. Watts

In even the most lucid literature on semi‐conductors, the complexity of electrons, holes, energy levels, acceptors, donors, and so on tends to swamp any understanding of…

Abstract

In even the most lucid literature on semi‐conductors, the complexity of electrons, holes, energy levels, acceptors, donors, and so on tends to swamp any understanding of the basic principles. This, we may say, is almost too difficult for us, so it is bound to be too difficult for our students. We then get round the problem by stating categorically that holes exist, that they have the properties of positive charge carriers, and leave it at that to get on to the circuitry.

Details

Education + Training, vol. 2 no. 10
Type: Research Article
ISSN: 0040-0912

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