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This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents.

In the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state.

The authors simulate the proposed circuit by using HSPICE in 45-nm CMOS technology for OR and AND logic gates such as OR2, OR4, OR8, AND2 and AND4 at 25°C and 110°C. The proposed circuit reduces leakage power consumption as compared to the existing circuits.

The proposed circuit significantly reduces the total leakage power consumption up to 99.41 and 99.51 per cent as compared to the standard dual-threshold voltage footless domino circuits at 25°C and 110°C, respectively, and up to 93.79 and 97.98 per cent as compared to the sleep control techniques at 25°C and 110°C, respectively. Similarly, the proposed circuit reduces the active power consumption up to 26.76 and 86.25 per cent as compared to the standard dual-threshold voltage and sleep control techniques footless domino circuits at 25°C and 110°C, respectively.

High head gates are commonly used in hydropower plants for flow regulation and emergence closure. Hydrodynamic downpull can be a critical parameter in design of the lifting mechanism. The purpose of this paper is to show that a simplified two-dimensional (2D) computational fluid dynamics solution can be used in the prediction of the downpull force on the gate lip by comparison of computed results to experimentally measured data.

In this study, ANSYS FLUENT CFD software was used to obtain 2D numerical solution for the flow field around a generic gate model located in a power intake structure which was previously used in an experimental study. Description of the flow domain, computational grid resolution, requirements on setting appropriate boundary conditions and methodology in describing downpull coefficient are discussed. Total number of 245 simulations for variable gate lip geometry and gate openings were run. The downpull coefficient evaluated from the computed pressure field as function of gate opening and lip angle are compared with the experimental results.

The computed downpull coefficient agrees well with the previous experimental results, except one gate with small lip angle where a separation bubble forms along the lip, which is responsible from this deviation. It is observed that three-dimensional (3D) effects are confined to the large gate openings where downpull is minimum or even reversed.

In large gate openings, three dimensionality of the flow around gate slots plays an important role and departure from 2D solutions become more pronounced. In that case, one might need to perform a 3D solution instead.

This paper presents a very fast and accurate way to predict downpull force on high head gates in the absence of experimental data.

An extensive amount of simulations are run within the scope of this study. It is shown that knowing its limitations, 2D numerical models can be used to calculate downpull for a wide range of gate openings without the need of expensive experimental models.

The purpose of this paper is to analyze the effects of scaling on the impact ionization and subthreshold current in submicron MOSFETs.

The effects of the various scaling techniques on a 100 nm device performances and the dependence of subthreshold current parameters on applied scaling technique are analyzed.

The results show that as the channel length is scaled down, multiplication factor increases slowly in the higher regime and rises rapidly in the lower regime of channel length. This result also justifies the inclusion of impact‐ionization effect on subthreshold current. The analysis shows that there is insignificant dependence of multiplication factor on the method of scaling. Similar variations in subthreshold current with channel length scaling have been observed in the analytical results for different scaling techniques.

The paper offers insight into the challenges of MOSFET scaling.

This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell.

The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate.

Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively.

The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

Cross tables are omnipresent in management, academia and popular culture. The Matrix has us, despite all criticism, opposition and desire for a way out. This paper draws on the works of three agents of the matrix. The paper shows that Niklas Luhmann criticised Talcott Parsons’ traditional matrix model of society and proceeded to update systems theory, the latest version of which is coded in the formal language of George Spencer Brown. As Luhmann failed to install his updates to all components of his theory platform, however, regular reoccurrences of Parsonian crosstabs are observed, particularly in the Luhmannian differentiation theory, which results in compatibility issues and produces error messages requesting updates. This paper aims to code the missing update translating the basic matrix structure from Parsonian into Spencer Brownian formal language.

This paper draws on work by Boris Hennig and Louis Kauffman and a yet unpublished manuscript by George Spencer Brown, to demonstrate that the latter introduced his cross as a mark to indicate NOR gates in circuit diagrams. The paper also shows that this NOR gate marker has been taken out of and may be observed to contain the tetralemma, an ancient matrix structure already present in traditional Indian logic. It then proceeds to translate the basic structure of traditional contingency tables into a Spencer Brownian NOR equation and to demonstrate the difference this translation makes in the modelling of social systems.

The translation of cross tables from Parsonian into Spencer Brownian formal language results in the design of a both matrix-shaped and compatible test routine that works as a virtual window for the observation of the actually unobservable medium in which a form is drawn, and can be used for consistency checks of expressions coded in Spencer Brownian formal language.

This paper quotes from and discusses a so far unpublished manuscript finalised by Spencer Brown in April 1961. The basic matrix structure is translated from Parsonian into Spencer Brownian formal language. A Spencer Brownian NOR matrix is coded that may be used to detect errors in expressions coded in Spencer Brownian formal language.

The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells.

This study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue.

The GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart.

Nano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit.

GNRFET devices are suitable for implementing low power and high density SRAM cell.

The conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices.

This paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.

The impacts of these interconnect process variations on circuit delay and cross‐talk noises along with the two major sources of delays – parametric delay variations and global interconnect delays – have been discussed.

Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and hence are non‐deterministic.

This paper usefully reviews process variation effects on very large‐scale integration (VLSI) interconnect.