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The purpose of this paper is to develop analytical model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET with inevitable nano scale effects (NSE).

A computationally efficient model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET in nano scale is presented. The model predictions are compared with the two‐dimensional Sentaurus device simulation.

Good agreement between the model and experimental data was obtained. The model also shows good agreement when compared with Sentaurus simulation and available model. It is observed that neglecting NSE may lead to large error in the calculated gate tunneling current. The findings provide a guideline to the severity of NSE from the point of view of standby power consumption. It is found that temperature and substrate bias have almost negligible effect on gate tunneling current. The gate tunneling current variation with gate bias, gate oxide thickness and source/drain overlap region have also been assessed.

The present work is concentrated only on the gate leakage current and is useful for gate leakage analysis of the circuits.

The model so developed is conceptually simple, numerically efficient and can be used for circuit simulator.

NSE are considered while modeling the gate tunneling current through nano scale n‐channel MOSFET.

Choosing suitable high‐K gate dielectrics to reduce the off‐state leakage (I_off) by edge direct tunneling mechanism, demonstrating that the decreased I_off increase significantly when the gate dielectrics permittivity are above 25. The purpose of this paper is to report that HfSiON and HfLaO are promising gate dielectrics.

The off‐state gate current, drain current, and substrate current are investigated. The I_d‐V_gs characteristics for the 50 and 90 nm NMOSFET with various gate dielectrics are studied. Edge direct tunneling current (I_EDT) with various gate dielectrics including SiO₂, Si₃N₄ and HfO₂ are compared and this paper also examines the I_EDT with HfSiON and HfLaO gate dielectrics.

I_EDT prevails over conventional gate‐induced drain‐leakage current (I_GIDL), subthreshold leakage current (I_SUB), band‐to‐band tunneling current (I_BTBT) and it dominates off‐state leakage current. A large increase in off‐state leakage current occurs for smaller devices due to increase in I_EDT at high V_dd. Although I_EDT is decreased with increase in gate dielectrics permittivity K. The authors found fringing induced barrier lowering (FIBL) which could introduce significant off‐state leakage current for K>25. Fortunately, the I_EDT with HfSiON and HfLaO gate dielectrics which are two‐five orders of magnitude lower than that of SiO₂, furthermore, FIBL for HfSiON and HfLaO gate dielectrics are inconspicuous. Moreover, HfLaO and HfSiON have superior electrical performance and thermal stability.

Both edge direct tunneling and FIBL are considered to alternate high‐K gate dielectrics for nano‐scale MOSFET.

The purpose of this paper was to present the results of the three types of FG transistors that were investigated. The reliability issues of oxide thickness due to programming, fabrication defects and process variation may cause leakage currents and thus charge retention failure in the floating gate (FG).

The tunnelling and electron injection methods were applied to program FG devices of different lengths (180 and 350 nm) and coupling capacitor sizes. The drain current and threshold voltage changes were determined for both gate and drain voltage sweep. The devices were fabricated using IBM 130 nm process technology.

Current leakages are increasing with device scaling and reducing the charge retention time. During programming, charge traps may occur in the oxide and prevent further programming. Thus, the dominant factors are the reliability of oxide thickness to avoid charge traps and prevent current/charge leakages in the FG devices. The capacitive coupling (between the tunnelling and electron injection capacitors) may contribute to other reliability issues if not properly considered.

Although the results have raised further research questions, as revealed by certain reliability issues, they have shown that the use of FGs with nanoscale technology is promising and may be suitable for memory and switching applications.

The aim of this paper is to formulate the effect of the process variation on various leakage currents and subthreshold swing factor in FinFET devices. These variations cause a large spread in leakage power, since it is extremely sensitive to process variations, which in turn results in larger temperature variations across different dies.

Owing to large temperature variation within the die, the authors investigate the variation of various leakage currents with absolute die temperature.

The results obtained on the basis of the model are compared and contrasted with reported numerical and experimental results. A close match was found which validates the analytical approach.

The analytical modeling of subthreshold leakage current, subthreshold swing, gate leakage current and its variation with process parameters are carried out in this paper.

This paper aims to propose a new lector-based domino and examine it with inputs and clock signal combination in a 45-nm dual-threshold footerless domino circuit for reduced leakage current.

In this technique, p-type and n-type leakage control transistors (LCTs) are introduced between pull-up and pull-down networks, and the gate of one is controlled by the source of the other. A high-threshold transistor is used in the input for reducing gate oxide leakage current, which becomes dominant in nanometre technology. Simulations were based on a 45-nm BISM 4 model using an HSPICE simulator for proposed domino circuits.

The result shows that CHIL (clock high and input low) state is ineffective for lowering leakage current and the conventional CHIH (clock high and input high) state is only effective to suppress the leakage at low temperature for wide fan-in domino circuits. At high temperature, CLIL (clock low and input low) state is preferable to reduce the leakage current for low fan-in domino, but for high fan-in domino, CHIH state is preferred. The proposed circuit technique for AND2, OR2, OR4 and OR8 circuits reduces the active power consumption by 50.94 to 75.68 per cent and by 64.85 to 86.57 per cent at low and high die temperatures, respectively, when compared to the standard dual-threshold voltage domino logic circuits.

The research proposes a new leakage reduction technique used in domino circuits and also evaluates the state for leakage reduction which can be used for low-power dynamic circuits.

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

The purpose of this paper is to present an improved model based on center potential instead of surface potential which is physically more relevant and accurate. Also, additional analytic insights have been provided to make the model independent and robust so that it can be extended to a full range compact model.

The design methodology used is center potential based analytical modeling using Psuedo-2D Poisson equation, with ingeniously developed boundary conditions, which help achieve reasonably accurate results. Also, the depletion width calculation has been suitably remodeled, to account for proper physical insights and accuracy.

The proposed model has considerable accuracy and is able to correctly predict most of the physical phenomena occurring inside the broken gate Tunnel FET structure. Also, a good match has been observed between the modeled data and the simulation results. I_on/I_ambipolar ratio of 10^(−8) has been achieved which is quintessential for low power SOCs.

The modeling approach used is different from the previously used techniques and uses indigenous boundary conditions. Also, the current model developed has been significantly altered, using very simple but intuitive technique instead of complex mathematical approach.

Theoretical calculations of tunneling characteristics of the Gated Resonant Tunneling Diode (GRTD) aie obtained in low dimensionality using a scattering transfer matrix approach. In the bias conditions whereby the GRTD reaches zero‐dimension in the well region, we consider attractive and repulsive perturbation potential (Vsc) of impurity or defect scattering in emitter and well regions. We describe the scattering matrices using the presence of evanescent, or nonpropagating, modes in different lateral confinement structure. Numerical solutions to the two‐dimensional Poisson equation and the continuity equation are used to calculate the lateral depletion region and carrier concentrations by the finite difference method. Electron transport in double‐barrier structure is calculated by a self‐consistent approach.

The purpose of this paper is to electrically examine the quality of thin thermally grown SiO₂ with thickness variation, on Si‐face of 4H‐SiC <0001> (having 50 μm epitaxial layer) by current‐voltage (I‐V) and capacitance‐voltage (C‐V) methods.

Metal‐oxide‐silicon carbide (MOSiC) structures with varying oxide thickness have been fabricated on device grade 4H‐SiC substrate. Ni has been used for gate metal on thermally oxidized Si‐face and a composite layer of Ti‐Au has been used for Ohmic contact on the highly doped C‐face of the substrate. Each structure was diced and bonded on a TO‐8 header with a suitable wire bonding for further testing using in‐house developed LabVIEW‐based computer aided measurement setup.

The leakage current of fabricated structures shows an asymmetric behavior with the polarity of gate bias ( + V or −V at the anode). A strong relation of oxide thickness and temperature on effective barrier height at SiO₂/4H‐SiC interface as well as on oxide charges have been established and reported in this paper.

The paper focuses on the development of 4H‐SiC based device technology in the fabrication of MOSiC‐based integrated structures.

Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels.

The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented.

The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%.

The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.