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The purpose of this paper is to develop analytical model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET with inevitable nano scale effects (NSE).

A computationally efficient model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET in nano scale is presented. The model predictions are compared with the two‐dimensional Sentaurus device simulation.

Good agreement between the model and experimental data was obtained. The model also shows good agreement when compared with Sentaurus simulation and available model. It is observed that neglecting NSE may lead to large error in the calculated gate tunneling current. The findings provide a guideline to the severity of NSE from the point of view of standby power consumption. It is found that temperature and substrate bias have almost negligible effect on gate tunneling current. The gate tunneling current variation with gate bias, gate oxide thickness and source/drain overlap region have also been assessed.

The present work is concentrated only on the gate leakage current and is useful for gate leakage analysis of the circuits.

The model so developed is conceptually simple, numerically efficient and can be used for circuit simulator.

NSE are considered while modeling the gate tunneling current through nano scale n‐channel MOSFET.

The aim of this paper is to formulate the effect of the process variation on various leakage currents and subthreshold swing factor in FinFET devices. These variations cause a large spread in leakage power, since it is extremely sensitive to process variations, which in turn results in larger temperature variations across different dies.

Owing to large temperature variation within the die, the authors investigate the variation of various leakage currents with absolute die temperature.

The results obtained on the basis of the model are compared and contrasted with reported numerical and experimental results. A close match was found which validates the analytical approach.

The analytical modeling of subthreshold leakage current, subthreshold swing, gate leakage current and its variation with process parameters are carried out in this paper.

The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors.

This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-sensing circuitry has been designed using 5-μm CMOS technology. The pressure-sensing structure consists of three identical 10-μm-long and 50-μm-wide n-channel MOSFETs connected in current mirror configuration, with its input transistor as a reference MOSFET and output transistors are the pressure-sensing MOSFETs embedded at the centre and near the fixed edge of a silicon diaphragm measuring 100 × 100 × 2.5 μm. This arrangement of MOSFETs enables the sensor to sense tensile and compressive stresses, developed in the diaphragm under externally applied pressure, with respect to the input reference transistor of the mirror circuit. An analytical model describing the complete behaviour of the integrated pressure sensor has been described. The simulation results of the pressure sensor show high pressure sensitivity and a good agreement with the theoretical model has been observed. A five mask level process flow for the fabrication of the current mirror-sensing-based pressure sensor has also been described. An n-channel MOSFET with aluminium gate was fabricated to verify the fabrication process and obtain its electrical characteristics using process and device simulation software. In addition, an aluminium gate metal-oxide semiconductor (MOS) capacitor was fabricated on a two-inch p-type silicon wafer and its CV characteristic curve was also measured experimentally. Finally, the paper presents a comparative study between the current mirror pressure-sensing circuit with the traditional Wheatstone bridge.

The simulated sensitivities of the pressure-sensing MOSFETs of the current mirror-integrated pressure sensor have been found to be approximately 375 and 410 mV/MPa with respect to the reference transistor, and approximately 785 mV/MPa with respect to each other. The highest pressure sensitivities of a quarter, half and full Wheatstone bridge circuits were found to be approximately 183, 366 and 738 mV/MPa, respectively. These results clearly show that the current mirror pressure-sensing circuit is comparable and better than the traditional Wheatstone bridge circuits.

The concept of using a basic current mirror circuit for sensing tensile and compressive stresses developed in micro-mechanical structures is new, fully compatible to standard CMOS processes and has a promising application in the development of miniaturized integrated micro-sensors and sensor arrays for automobile, medical and industrial applications.

Choosing suitable high‐K gate dielectrics to reduce the off‐state leakage (I_off) by edge direct tunneling mechanism, demonstrating that the decreased I_off increase significantly when the gate dielectrics permittivity are above 25. The purpose of this paper is to report that HfSiON and HfLaO are promising gate dielectrics.

The off‐state gate current, drain current, and substrate current are investigated. The I_d‐V_gs characteristics for the 50 and 90 nm NMOSFET with various gate dielectrics are studied. Edge direct tunneling current (I_EDT) with various gate dielectrics including SiO₂, Si₃N₄ and HfO₂ are compared and this paper also examines the I_EDT with HfSiON and HfLaO gate dielectrics.

I_EDT prevails over conventional gate‐induced drain‐leakage current (I_GIDL), subthreshold leakage current (I_SUB), band‐to‐band tunneling current (I_BTBT) and it dominates off‐state leakage current. A large increase in off‐state leakage current occurs for smaller devices due to increase in I_EDT at high V_dd. Although I_EDT is decreased with increase in gate dielectrics permittivity K. The authors found fringing induced barrier lowering (FIBL) which could introduce significant off‐state leakage current for K>25. Fortunately, the I_EDT with HfSiON and HfLaO gate dielectrics which are two‐five orders of magnitude lower than that of SiO₂, furthermore, FIBL for HfSiON and HfLaO gate dielectrics are inconspicuous. Moreover, HfLaO and HfSiON have superior electrical performance and thermal stability.

Both edge direct tunneling and FIBL are considered to alternate high‐K gate dielectrics for nano‐scale MOSFET.

As the physical dimensions of the devices are reduced to the submicrometer regime, the hot‐carrier reliability has become an important issue in the scaling of the p‐MOSFET as well as the n‐MOSFET. In this paper, we present a unified approach for p‐MOSFET degradation due to the trapping of the hot electrons in the gate oxide layers. A physical analytical model, based on the pseudo two‐dimensional model, is derived for the first time to describe the linear and saturation drain current degradation. The model has been verified by comparing the calculation and the measurement from submicron p‐MOSFET's with different channel lengths and oxide thickness. There are no empirical parameters in the model. Two physical parameters: the capture cross section and the density of states of electron traps, which can be determined independently from the measured degradation characteristics, are valid for both the linear current and the saturation current degradation. The simple expression is very suitable for the predicting of the circuit reliability.

This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents.

In the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state.

The authors simulate the proposed circuit by using HSPICE in 45-nm CMOS technology for OR and AND logic gates such as OR2, OR4, OR8, AND2 and AND4 at 25°C and 110°C. The proposed circuit reduces leakage power consumption as compared to the existing circuits.

The proposed circuit significantly reduces the total leakage power consumption up to 99.41 and 99.51 per cent as compared to the standard dual-threshold voltage footless domino circuits at 25°C and 110°C, respectively, and up to 93.79 and 97.98 per cent as compared to the sleep control techniques at 25°C and 110°C, respectively. Similarly, the proposed circuit reduces the active power consumption up to 26.76 and 86.25 per cent as compared to the standard dual-threshold voltage and sleep control techniques footless domino circuits at 25°C and 110°C, respectively.

The purpose of this paper is to report the effect of sputtering time on the electrical and physical properties of ZrO_x. ZrO_x (measured thickness is ranging from 20.5 to 51.3 nm) thin films as gate oxide materials are formed by metal deposition at different sputtering time and thermal oxidation techniques.

Zirconium is deposited on silicon substrate at three different sputtering time; 30‐, 60‐ and 120‐s continued with an oxidation process conducted at 500°C for 15 min to form ZrO_x thin films. High‐resolution X‐ray diffraction (HR‐XRD), Fourier transform infrared (FTIR) spectroscopy and electrical characterizations were used to examine the properties of the thin film.

A broad ZrO_x peak lies in between 26° and 31° from HR‐XRD is presumed as the effect of small thickness of ZrO_x and or the ZrO_x is still partially crystalline. FTIR spectroscopy results suggested that besides ZrO_x, SiO_x interfacial layer (IL) has also formed in all of the investigated samples. As the sputtering time increases, hysteresis between the forward and reverse bias of capacitance‐voltage curve has reduced. The lowest leakage current density and the highest oxide breakdown voltage have been demonstrated by 60‐s sputtered sample. These may be attributed to a lower effective oxide charge and interface trap density. The extracted dielectric constant (κ) of these oxides is ranging from 9.4 to 18, in which the κ value increases with the increase in sputtering time.

ZrO_x thin film which was fabricated by sputtering method at different sputtering time and thermal oxidation techniques showed distinctive electrical results. SiO_x IL formed in the samples.

To study the breakdown (MI) mechanism in the sub‐micron MOSFET device.

Second‐order Poisson's differential equation is solved for suitable boundary condition to find the electric field expression for the sub‐micron devices. With the help of the electric field expression the exact relation for multiplication factor is derived, and then the equation for breakdown voltage has been generated.

This research paper provides the following findings: by controlling oxide thickness, junction depth and drain voltage, the breakdown can be easily controlled in the sub‐micron device; multiplication factor is not only affected by maximum field but also due to critical field; for very low gate voltage, the offset voltage mainly governs the breakdown; the breakdown voltage increases continuously as the channel length increases. It means, for larger channel length the breakdown will occur at high drain voltage.

This paper is based on the assumption that the electric field along the channel is independent of the junction depth (although not correct) and varying linearly from zero to E_sat.

The paper derived the exact expression of the multiplication factor. Also discusses that for MI mode of breakdown, the breakdown voltage increases slowly with the gate voltage and approximated by drain saturation voltage plus offset voltage.

This study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs.

This paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach.

It is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement.

Compact Analytical models for undoped symmetric double gate MOSFETs.

Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.

The impacts of these interconnect process variations on circuit delay and cross‐talk noises along with the two major sources of delays – parametric delay variations and global interconnect delays – have been discussed.

Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and hence are non‐deterministic.

This paper usefully reviews process variation effects on very large‐scale integration (VLSI) interconnect.