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The purpose of this paper is to develop analytical model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET with inevitable nano scale effects (NSE).

A computationally efficient model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET in nano scale is presented. The model predictions are compared with the two‐dimensional Sentaurus device simulation.

Good agreement between the model and experimental data was obtained. The model also shows good agreement when compared with Sentaurus simulation and available model. It is observed that neglecting NSE may lead to large error in the calculated gate tunneling current. The findings provide a guideline to the severity of NSE from the point of view of standby power consumption. It is found that temperature and substrate bias have almost negligible effect on gate tunneling current. The gate tunneling current variation with gate bias, gate oxide thickness and source/drain overlap region have also been assessed.

The present work is concentrated only on the gate leakage current and is useful for gate leakage analysis of the circuits.

The model so developed is conceptually simple, numerically efficient and can be used for circuit simulator.

NSE are considered while modeling the gate tunneling current through nano scale n‐channel MOSFET.

The aim of this paper is to formulate the effect of the process variation on various leakage currents and subthreshold swing factor in FinFET devices. These variations cause a large spread in leakage power, since it is extremely sensitive to process variations, which in turn results in larger temperature variations across different dies.

Owing to large temperature variation within the die, the authors investigate the variation of various leakage currents with absolute die temperature.

The results obtained on the basis of the model are compared and contrasted with reported numerical and experimental results. A close match was found which validates the analytical approach.

The analytical modeling of subthreshold leakage current, subthreshold swing, gate leakage current and its variation with process parameters are carried out in this paper.

An empirical velocity‐field relationship, based on Monte Carlo simulation, is used to modify a drift‐diffusion model for the characterization of short gate GaAs MESFET's. The modified drift‐diffusion model is used to generate both the steady‐state and the small‐signal parameters of submicron GaAs MESFET's. The current, transconductance, and cutoff frequency are compared with two‐dimensional Monte Carlo simulation results on a 0.2 µm gate‐length. The model is also used to predict measured I‐V and s‐parameters of a 0.5 µm gate‐length ion‐implanted GaAs MESFET. The comparison and the analysis made, support the accuracy of the modified drift‐diffusion simulator and makes it computationally efficient for analysis of short‐gate devices.

The purpose of this paper is to present an improved model based on center potential instead of surface potential which is physically more relevant and accurate. Also, additional analytic insights have been provided to make the model independent and robust so that it can be extended to a full range compact model.

The design methodology used is center potential based analytical modeling using Psuedo-2D Poisson equation, with ingeniously developed boundary conditions, which help achieve reasonably accurate results. Also, the depletion width calculation has been suitably remodeled, to account for proper physical insights and accuracy.

The proposed model has considerable accuracy and is able to correctly predict most of the physical phenomena occurring inside the broken gate Tunnel FET structure. Also, a good match has been observed between the modeled data and the simulation results. I_on/I_ambipolar ratio of 10^(−8) has been achieved which is quintessential for low power SOCs.

The modeling approach used is different from the previously used techniques and uses indigenous boundary conditions. Also, the current model developed has been significantly altered, using very simple but intuitive technique instead of complex mathematical approach.

The purpose of this paper is to explore and evaluate the performance comparison of carbon nanotubes (CNT) and nickel silicide (NiSi) nanowires interconnects as prospective alternatives to copper wire interconnects.

The increasing resistivity of the copper wire with scaling and rising demands on current density drives the need for identifying new wiring solutions. This paper explores the various alternatives to copper. The metallic bundle CNTs and NiSi nanowires are promising candidates that can potentially address the challenges faced by copper. This paper analyzes various electrical models of carbon nanotube and recently introduced novel interconnect solution using NiSi nanowires.

The theoretical studies proves CNTs and NiSi nanowires to be better alternatives against copper on the ground of performance parameters, such as effective current density, delay and power consumption. NiSi nanowire provides highest propagation speed for short wire length, and copper is the best for intermediate wire length, while bundle CNTs is faster for long wire length. NiSi nanowire has lowest power consumption than copper and CNTs.

This paper investigates, assess and compares the performance of carbon nanotubes (CNT) and NiSi nanowires interconnects as prospective alternatives to copper wire interconnects in future VLSI chips.

The purpose of this paper is to report upon high power, internally matched GaN high electron mobility transistors (HEMTs) at Ku band with 1.5 GHz bandwidth, which employ a simple and cost‐effective lossless compensated matching technique.

Two 4 mm gate periphery GaN HEMTs are parallel combined and internally matched with multi‐section reactive impedance transformers at the input and output networks. The output matching network is designed at the upper frequency of the design band for a flat power of the circuit, while the input matching network is designed at the upper frequency for a flat gain.

With the reactively compensated matching technique, the internally matched GaN HEMTs exhibit a flat saturated output power of 43.2+0.7 dBm and an average power added efficiency of 15 per cent over 12 to 13.5 GHz.

This paper provides useful information for the internally matched GaN HEMTs.

The use of energy balance and simplified hydrodynamic models for simulating GaAs devices is investigated. The simplified hydrodynamic model predicts velocity spikes that are not present in more detailed Monte Carlo simulation results. These velocity spikes are associated with overestimation of thermal diffusion. The simplified hydrodynamic model can predict terminal currents that are significantly lower than those predicted by the energy balance model. The differences between the models are significantly greater than those observed previously for silicon devices. The main conclusion of this study is that the energy balance model is preferable to the simplified hydrodynamic model as the basis for GaAs device simulation, but the energy balance model still needs refinement to improve the agreement with more general simulation and experimental results.

Choosing suitable high‐K gate dielectrics to reduce the off‐state leakage (I_off) by edge direct tunneling mechanism, demonstrating that the decreased I_off increase significantly when the gate dielectrics permittivity are above 25. The purpose of this paper is to report that HfSiON and HfLaO are promising gate dielectrics.

The off‐state gate current, drain current, and substrate current are investigated. The I_d‐V_gs characteristics for the 50 and 90 nm NMOSFET with various gate dielectrics are studied. Edge direct tunneling current (I_EDT) with various gate dielectrics including SiO₂, Si₃N₄ and HfO₂ are compared and this paper also examines the I_EDT with HfSiON and HfLaO gate dielectrics.

I_EDT prevails over conventional gate‐induced drain‐leakage current (I_GIDL), subthreshold leakage current (I_SUB), band‐to‐band tunneling current (I_BTBT) and it dominates off‐state leakage current. A large increase in off‐state leakage current occurs for smaller devices due to increase in I_EDT at high V_dd. Although I_EDT is decreased with increase in gate dielectrics permittivity K. The authors found fringing induced barrier lowering (FIBL) which could introduce significant off‐state leakage current for K>25. Fortunately, the I_EDT with HfSiON and HfLaO gate dielectrics which are two‐five orders of magnitude lower than that of SiO₂, furthermore, FIBL for HfSiON and HfLaO gate dielectrics are inconspicuous. Moreover, HfLaO and HfSiON have superior electrical performance and thermal stability.

Both edge direct tunneling and FIBL are considered to alternate high‐K gate dielectrics for nano‐scale MOSFET.

Truck appointment systems have been applied in critical container ports in the United States due to their potential to improve handling operations. This paper aims to develop a truck appointment system to optimise the total cost experiencing at the entrance of container terminals by managing truck arrivals and the number of service gates satisfying a given level of service.

The approximation of M_t/G/n_t queuing model is applied and integrated into a cost optimisation model to identify (1) the number of arrival trucks allowed at each time slot and (2) the number of service gates operating at each time slot that ensure the average waiting time is less than a designated time threshold. The optimisation model is solved by the Genetic Algorithm and tested with a case study. Its effectiveness is identified by comparing the model's outcomes with observed data and other recent studies.

The results indicate that the developed truck appointment system can provide more than threefold and twofold reductions of the total cost experiencing at the terminal entrance compared to the actual data and results from previous research, respectively.

The proposed approach provides applicably coordinated truck plans and operating service gates efficiently to decrease congestion, emission and expenses.

Effects of lattice temperature on MOSFET characteristics and a rough distribution of carrier temperature, are studied using a non‐isothermal device simulator which also includes the effect of temperature gradient on the current density. To clarify the mechanism of the increase in lattice temperature, the source of heat generation is investigated. We have confirmed that the increase in lattice temperature results mainly from the generation of Joule heat, representing the product of the electric field and the electron current density. We also found that, as the gate length becomes short, the lattice temperature rises exponentially. In addition, it is found that the lattice temperature shows a localized increase of 77 degrees under normal biasing conditions in the MOSFET with a gate length of 0.5[ μ m].