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Numerical techniques and experimental methods for the electrical characterisation and design of large multilayer thick film circuit boards are discussed. The numerical techniques investigated here include the boundary element and finite element methods for the estimation of capacitance and inductance and the method of normal modes for the analysis of voltage crosstalk between coupled transmission lines. Three‐dimensional capacitance and inductance calculations are included for typical thick film signal line and power and ground grid plane configurations. Numerical results are compared with measured data obtained from carefully constructed test coupons. Electrical characteristics of several popular high speed logic families and their compatibility with multilayer thick film interconnects are discussed and guidelines for the design of large thick film circuit boards for high speed digital applications are presented.

The challenge presented by advanced package development in the past five years has further accentuated the constant need for package quality and reliability monitoring through extensive laboratory testing and evaluation. As pin counts and chip geometries have continued to increase, there has been additional pressure from the military and commercial sectors to improve interconnect designs for packaged chips, including chips directly attached to the printed wiring board (PWB). One of the options employed has been tape automated bonding (TAB). However, this assembly technique also presents new standardisation, qualification and reliability problems. Therefore, at Rome Air Development Center (RADC), there is regular assessment (through in‐house failure analysis studies) of parts destined for military and space systems. In addition, Department of Defense (DoD) high tech development programmes, such as very high speed integrated circuits (VHSIC), have utilised all present screening methods for package evaluation, and have addressed the need for development of more definitive non‐destructive tests. To answer this need, two RADC contractual efforts were awarded on laser thermal and ultrasonic inspection techniques. Through these package evaluations, a number of potential reliability problems are identified and the results provided to the specific contractors for corrective action implementation. Typical problems uncovered are lid material and pin corrosion, damage to external components and adhesion problems between copper leads and polyimide supports, hermeticity failures, high moisture content in sealed packages and particle impact noise detection (PIND) test failures (internal particles). Further tests uncover bond strength failures, bond placement irregularities, voids in die attach material (potential heat dissipation problems), and die surface defects such as scratches and cracks. This presentation will review the specific package level physical test methods that are employed as a means of evaluating reliable package performance. Many of the tests, especially the environmental tests—e.g., salt atmosphere and moisture resistance—provide accelerated forms of anticipated conditions and are therefore applied as destructive tests to assess package quality and reliability in field use. In addition to a manufacturer's compliance with designated qualification procedures, the key to package quality lies in utilising good materials and well‐controlled assembly techniques. This practice, along with effective package screen tests, will ensure reliable operation of very large scale integration (VLSI) devices in severe military and commercial environment applications.

Computer algebra or symbolic manipulation is nothing else than performing analytical calculations with the help of a computer. This offers the advantage that lengthy and complicated calculations can be carried out without errors in a very short time. Computer algebra techniques have also been applied to solve electrical networks. This offers particular advantages for hybrid circuit design, as will be outlined extensively in this paper.

An attempt is made to discuss the adhesion of thick film conductors on ceramic substrates in connection with thermally induced internal stresses caused by mismatch of the thermal expansion coefficient of the various layers and the substrate. The curvature of the bent substrates was taken as a measure of the internal stresses. A theoretical multilayer model is proposed for description of the composite — substrate/conductor/solder/intermetallic phases. This permits estimation of the stresses and the Young's modulus within the layers and explains the decrease of adhesion of the soldered copper layer after ageing.

The once highly publicised Porcelain Enamelled Steel (PES) substrates seem to have disappeared from the public gaze, or have they? They certainly have not. If anything, they have consolidated their place in electronics applications and are growing in use at a remarkable pace in particular applications supplied by the major USA source, namely Ferro‐ECA.

The Benelux chapter has made a habit of organising meetings with a scientific and commercial accent more or less alternately. This approach has proven to be successful in the past three years. The 1986 Autumn meeting will be another display meeting. A number of papers will be presented by suppliers of materials and equipment for the hybrid and surface mounting industry. In a 300 m2 exhibition room about 25 companies will display their products. The programme of the day leaves ample opportunity for meeting colleagues and suppliers. The meeting will be held in the ‘Jaarbeurs Vergadercentrum’ in Utrecht on 16 October from 9.30–17.00. The annual ISHM‐Benelux general membership meeting will precede the lectures.

The ageing behaviour of aluminium wire bonds (Al‐1%Si wire, 25 µm diameter) on five different gold thick film inks from three different manufacturers has been investigated. A new mechanism, the oxidation of the gold‐aluminium intermetallics, is proposed to explain the degradation of contact resistance for this system. With this theory the degradation of bond resistance, as well as the ‘healing effect’, can be explained. The oxidation can be proven by ageing in a vacuum. Surface analytical methods have shown the compound Au4Al to be responsible for the oxidation.

In this paper, the process of forming copper wire balls in copper ball bonding has been studied by numerical analysis. By calculating the temperature field, speed field and displacement field for ultra‐fine copper wire under a miniarc, a regular pattern of copper wire ball formation has been observed. The calculation results for the displacement field has also been tested and verified.

An overview of the concerns involved in the operation of electronic hardware at elevated temperatures is presented. Materials selection and package design issues are addressed for a wide range of packaging elements from the semiconductor chip to the box. It is found that most elements of common high density device and packaging architecture can be used up to 200°C. However, gold‐aluminium wirebonds, eutectic tin‐lead solder joints and die attaches, and FR‐4 boards will seriously degrade at temperatures below 200°C. For these elements, alternative materials of construction are recommended. Comparisons are made between package design for high power dissipation and that for high temperature operation.

Although men's studies is no longer a novelty on college campuses, it can still raise some bewildered eyebrows and prompt a few explosive reactions. Recently, on a national computer bulletin board used by reference librarians, a request for journals, articles, and books “that analyze drama from a male/masculine perspective” touched off considerable crossfire among respondents. Beneath the hostilities, however, were serious questions and understandable confusions about the topic of men's studies. These concerns suggest that some clarifications concerning the new men's studies might be useful.