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The purpose of this paper is to analyze and forecast the Chinese term structure of interest rates using functional principal component analysis (FPCA).

The authors propose an FPCA-K model using FPCA. The forecasting of the yield curve is based on modeling functional principal component (FPC) scores as standard scalar time series models. The authors evaluate the out-of-sample forecast performance using the root mean square and mean absolute errors.

Monthly yield data from January 2002 to December 2016 are used in this paper. The authors find that in the full sample, the first two FPCs account for 98.68 percent of the total variation in the yield curve. The authors then construct an FPCA-K model using the leading principal components. The authors find that the FPCA-K model compares favorably with the functional signal plus noise model, the dynamic Nelson-Siegel models and the random walk model in the out-of-sample forecasting.

The authors propose a functional approach to analyzing and forecasting the yield curve, which effectively utilizes the smoothness assumption and conveniently addresses the missing-data issue.

To the best knowledge, the authors are the first to use FPCA in the modeling and forecasting of yield curves.

This study proposes targeted modernization of the Department of Defense (DoD's) Joint Forces Ammunition Logistics information system by implementing the optimized innovative information technology open architecture design and integrating Radio Frequency Identification Device data technologies and real-time optimization and control mechanisms as the critical technology components of the solution. The innovative information technology, which pursues the focused logistics, will be deployed in 36 months at the estimated cost of $568 million in constant dollars. We estimate that the Systems, Applications, Products (SAP)-based enterprise integration solution that the Army currently pursues will cost another $1.5 billion through the year 2014; however, it is unlikely to deliver the intended technical capabilities.

The purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.

In the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.

The effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.

This paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.

A fast identification algorithm for a linear monotonic process from a step response is proposed in this paper, from which the parameters of a first‐order plus dead‐time model can be obtained directly.

The study is based on a non‐asymptotic distributional estimation technique initiated without delay in the framework of systems. Such a technique leads to simple realization schemes, involving integrators, multipliers and piecewise polynomial or exponential time functions and shows a possible link between simultaneous identification and generalized eigenvalue problems. Thus, it allows for a real‐time implementation.

The effectiveness of the identification method has been demonstrated through a number of simulation examples and a real‐time test.

This paper presents a novel method to simultaneous delay and parameters identification of a stable first‐order plus time delay model from step response that can model a widespread class of systems.

In this article, we survey experiments that are directly related to monetary policy and central banking. We argue that experiments can also be used as a tool for central bankers for bench testing policy measures or rules. We distinguish experiments that analyze the reasons for non-neutrality of monetary policy, experiments in which subjects play the role of central bankers, experiments that analyze the role of central bank communication and its implications, experiments on the optimal implementation of monetary policy, and experiments relevant for monetary policy responses to financial crises. Finally, we mention open issues and raise new avenues for future research.

One crucial but sometimes overlooked fact regarding the difference between observation in the cross-section and observation over time must be stated before proceeding further. Tempting though it is to draw conclusions about the dynamics of a process from cross-sectional observations taken as a snapshot of that process, it is a fallacious practice except under a very precise condition that is highly unlikely to obtain in processes of interest to the social scientist. That condition is known as ergodicity.

Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.

The impacts of these interconnect process variations on circuit delay and cross‐talk noises along with the two major sources of delays – parametric delay variations and global interconnect delays – have been discussed.

Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and hence are non‐deterministic.

This paper usefully reviews process variation effects on very large‐scale integration (VLSI) interconnect.

Examines the thirteenth published year of the ITCRR. Runs the whole gamut of textile innovation, research and testing, some of which investigates hitherto untouched aspects. Subjects discussed include cotton fabric processing, asbestos substitutes, textile adjuncts to cardiovascular surgery, wet textile processes, hand evaluation, nanotechnology, thermoplastic composites, robotic ironing, protective clothing (agricultural and industrial), ecological aspects of fibre properties – to name but a few! There would appear to be no limit to the future potential for textile applications.