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As a result of the trend towards portable communication products, low‐cost miniaturisation is becoming increasingly important. One of the methods to achieve low‐cost…
As a result of the trend towards portable communication products, low‐cost miniaturisation is becoming increasingly important. One of the methods to achieve low‐cost miniaturisation is flip‐chip assembly on FR4 boards. In this paper, two types of flip‐chip assembly process will be discussed: a process where flip‐chips with eutectic solder‐bumps are assembled by using a tacky flux, and a process where flip‐chips are assembled by using solder paste. Both processes have been verified on production boards, using production equipment. Demonstrated ppm defect levels are between 35 and 400 ppm (confidence level 95 per cent) at the solder joint level. Component yields for flip‐chips are between 99.2 and 100 per cent. The reliability of the assemblies fulfils consumer communication equipment requirements.
The relentless drive towards greater complexity and interconnection density on silicon integrated circuit (SIC) devices is leading to a reappraisal of techniques for…
The relentless drive towards greater complexity and interconnection density on silicon integrated circuit (SIC) devices is leading to a reappraisal of techniques for making electrical connections from the SIC to the next level of packaging. The techniques being examined include fine pitch Wire Bonding, Tape Automated Bonding (TAB) and Flip‐chip Solder Bonding. This latter technique forms the subject of this paper. The history of flip‐chip solder bonding technology is briefly reviewed and metallurgical, physical and mechanical aspects of the bonding process and of the resulting joints are discussed. The merits of the flip‐chip bonding process are indicated and applications examples presented. Particular attention is given to the fabrication of a novel pyroelectric‐SIC thermal imaging sensor using flip‐chip solder bonding.
This paper aims to present an integrated optimisation‐modelling computational approach for virtual prototyping that helps design engineers to improve the reliability and…
This paper aims to present an integrated optimisation‐modelling computational approach for virtual prototyping that helps design engineers to improve the reliability and performance of electronic components and systems through design optimisation at the early product development stage. The design methodology is used to identify the optimal design of lead‐free (Sn3.9Ag0.6Cu) solder joints in fine‐pitch copper column bumped flip‐chip electronic packages.
The design methodology is generic and comprises numerical techniques for computational modelling (finite element analysis) coupled with numerical methods for statistical analysis and optimisation. In this study, the integrated optimisation‐modelling design strategy is adopted to prototype virtually a fine‐pitch flip‐chip package at the solder interconnect level, so that the thermal fatigue reliability of the lead‐free solder joints is improved and important design rules to minimise the creep in the solder material, exposed to thermal cycling regimes, are formulated. The whole prototyping process is executed in an automated way once the initial design task is formulated and the conditions and the settings for the numerical analysis used to evaluate the flip‐chip package behaviour are specified. Different software modules that incorporate the required numerical techniques are used to identify the solution of the design optimisation problem related to solder joints reliability optimisation.
For fine‐pitch flip‐chip packages with copper column bumped die, it is found that higher solder joint volume and height of the copper column combined with lower copper column radius and solder wetting around copper column have a positive effect on the thermo‐mechanical reliability.
The findings of this research provide design rules for more reliable lead‐free solder joints for copper column bumped flip‐chip packages and help to establish further the technology as one of the viable routes for flip‐chip packaging.
The IBM ceramic quad flat pack (CQFP) is a high performance, low‐costchip carrier for surface mount assembly. It is an extension of metallised ceramic (MC) andmetallised…
The IBM ceramic quad flat pack (CQFP) is a high performance, low‐cost chip carrier for surface mount assembly. It is an extension of metallised ceramic (MC) and metallised ceramic with polyimide (MCP) product technologies. These finished modules conform to JEDEC I/O and footprint standards. They are available in 0.5 mm and 0.4 mm lead pitches with flexibility to address unique application requirements such as body sizes or lead pitches. Connection from integrated circuit (IC) to carrier is performed using flip‐chip (C4 ‐ Controlled Collapse Chip Connection) attach. Silicon die size and the quantity of C4 connections for flip‐chip joining have historically been constrained to reduce early life failures caused by solder fatigue wearout. This DNP (distance from neutral point of chip footprint) limitation has been overcome with increasing usage of epoxy encapsulation as a flip‐chip underfill. The encapsulant matches the coefficient of thermal expansion (CTE) of C4 solder and minimises stresses on the interconnection. This enhancement provides a substantial reliability improvement in comparison with unencapsulated packages. Also, it enables larger die with smaller C4 solder bumps on finer pitches to be assembled on ceramic carriers. Recent product development and testing have extended flip‐chip on ceramic packaging technology even further than previously anticipated. Test die up to 20 mm in size with over 2,000 C4 joints have been successfully assembled, encapsulated, stress tested and qualified in CQEP modules. Flip‐chip assembly and encapsulation of C4 connections on very large die to CQFP components have been implemented into IBM manufacturing production. This large‐scale packaging enhancement continues to demonstrate that flip‐chip underfill eliminates the intrinsic failure mechanisms associated with fatigue wearout. This provides a significant technology extension to this low‐cost and high reliability product offering.
Reports the research and development results on flip chip on FR‐4 and ceramics, using anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or eutectic…
Reports the research and development results on flip chip on FR‐4 and ceramics, using anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or eutectic solder with underfill. Several types of ACF and ACP with different types of conductive particles and adhesives were investigated. Simple but high yield procedures for reworking flip chip on board using ACP and ACF were developed. Processes for flip chip on FR‐4 and ceramic boards using eutectic solder bumps with underfill were also evaluated. The flip chips were assembled on test vehicles for temperature cycling and high‐temperature high‐humidity tests. The reliability performance of the three processes (gold bumps with ACF, gold bumps with ACP, and eutectic solder bumps with underfill) is compared.
Theelectronics packaging industry is debating whether CSP, Chip Scale Packaging, or flip chip isgoing to become the major alternative for future products. The user wants…
The electronics packaging industry is debating whether CSP, Chip Scale Packaging, or flip chip is going to become the major alternative for future products. The user wants more functionality and portability at an ever increasing speed and the need for denser packaging is becoming urgent. The issue of acquiring adequate circuit boards is pressing. However, the comparison between CSP and flip chip is not straightforward, since many CSPs are really flip chips in small packages. CSPs therefore, do not compare with flip chip on board but with packaged die.
Many bumping techniques for flip‐chip interconnections have been developed based on sputtering and electrolytic plating processes. In order to allow bumping on single chips…
Many bumping techniques for flip‐chip interconnections have been developed based on sputtering and electrolytic plating processes. In order to allow bumping on single chips, a new approach is adopted. Suitable metallisation layers are obtained by chemical plating techniques; bump formation is achieved by wire bonding of lead base wires or reflow melting of atomised spherical powders (solder balls). Flip‐chip modules on silicon substrate are created after reflow soldering in vacuum or in vapour phase. The quality and reliability of the interconnections are characterised by scanning electron microscopy, shear testing, microhardness measurement, non‐destructive testing, temperature and power cycling. It is found that high strength, high quality flip‐chip interconnections can be achieved. The present method is also economically competitive in comparison with sputtering techniques for the formation of metallisation layers.
Most flip chip assemblies require underfill to bestow reliability that would otherwise be ravished by stress due to thermomechanical mismatch between die and substrate…
Most flip chip assemblies require underfill to bestow reliability that would otherwise be ravished by stress due to thermomechanical mismatch between die and substrate. While underfill can be viewed as “polymer magic” and the key to modern flip chip success, many see it as the process “bottleneck” that must be eliminated in the future. Both views are accurate. A substantial amount of R&D is being focused on making underfill more user‐friendly. Electronic materials suppliers, various consortia, government labs and university researchers are working diligently to shatter the bottleneck and fully enable flip chip ‐ the final destination for micropackaging. This paper will describe these efforts and provide a status report on state‐of‐the‐art underfill technologies. We will also examine new processing strategies.
Known good die, flip chip and chip scale packages are technologies that offer various advantages to the board manufacturer. A discussion of the different types of package options, their methods of assembly, test and performance comparisons can help to resolve the general direction a manufacturer might pursue for next generation systems. This paper attempts to give a perspective as well as highlighting the areas of concern with the different options.
A flip chip on board technology fully compatible with current PCB facilities is reported. It used reflow soldering for chip attachment. It required electroless…
A flip chip on board technology fully compatible with current PCB facilities is reported. It used reflow soldering for chip attachment. It required electroless nickel/immersion gold finishing on the board pads as well as on the chip pads. A no‐clean solder paste was printed on the boards before chip placement. Thus, there was no requirement for solder deposition on the chip side. Assembly tests with various chip formats proved the feasibility of this technology. X‐ray inspection and cross‐sectioning revealed the good shape and alignment of the reflowed solder joints. The reliability of underfilled assemblies was studied by ‐40 to 125°C thermal cycling. This approach is especially suitable for prototype or low volume productions as it eliminates the solder bumping process on the chip side, which is usually performed on the wafer level.