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As a result of the trend towards portable communication products, low‐cost miniaturisation is becoming increasingly important. One of the methods to achieve low‐cost miniaturisation is flip‐chip assembly on FR4 boards. In this paper, two types of flip‐chip assembly process will be discussed: a process where flip‐chips with eutectic solder‐bumps are assembled by using a tacky flux, and a process where flip‐chips are assembled by using solder paste. Both processes have been verified on production boards, using production equipment. Demonstrated ppm defect levels are between 35 and 400 ppm (confidence level 95 per cent) at the solder joint level. Component yields for flip‐chips are between 99.2 and 100 per cent. The reliability of the assemblies fulfils consumer communication equipment requirements.

The objective of this research is to address issues that relate to the assembly of Sn/Ag/Cu bumped flip chips.

Flip chips bumped with Sn/Ag/Cu bumps were assembled onto different lead‐free surface finishes at lead‐free soldering temperatures. Sensitivity to fluxes, reflow profiles, pad finishes and pad designs were all investigated and the potential consequences for assembly yields were calculated numerically.

Soldering defects, such as incomplete wetting and collapse and poor self‐centring were observed in the assemblies. Defect levels were sensitive to contact pad metallurgy and flux type, but not to flux level and reflow profile within the ranges considered. Owing to a particularly robust substrate‐pad design, defects observed in this work were limited to incomplete wetting and collapse, as well as poor self‐centering.

The scope of this work is limited to the lead‐free fluxes available at the time of research. A switch to lead‐free solder alloys in flip chip assemblies raises concerns with respect to the compatibilities of materials and the quality of soldering that is achievable. While this may be less of an issue in the case of larger area array components, such as ball grid arrays and chip scale packages, it is more of a concern for applications that use flip chips due to the smaller size of the solder spheres. Assembly yields tend to become more sensitive to the reduced collapse of the joints. More work is essential to investigate the potential benefits of more active lead‐free fluxes, both no‐clean tacky and liquid fluxes, in reducing or eliminating soldering defects.

The paper offers insights into assembly issues with Sn/Ag/Cu bumped flip chips.

This paper aims to introduce a new indicative parameter of filling efficiency to quantify the performance and productivity of the flip-chip underfill encapsulation process. Additionally, the variation effect of the bump pitch of flip-chip on the filling efficiency was demonstrated to provide insight for flip-chip design optimization.

The filling efficiency was formulated analytically based on the conceptual spatial and temporal perspectives. Subsequently, the effect of bump pitch on filling efficiency was studied based on the past actual-scaled and current scaled-up underfill experiments. The latter scaled-up experiment was validated with both the finite volume method-based numerical simulation and analytical filling time model. Moreover, the scaling validity of scaled-up experiment was justified based on the similarity analysis of dimensionless number.

Through the scaling analysis, the current scaled-up experimental system is justified to be valid since the adopted scaling factor 40 is less than the theoretical scaling limit of 270. Furthermore, the current experiment was qualitatively well validated with the numerical simulation and analytical filling time model. It is found that the filling efficiency increases with the bump pitch, such that doubling the bump pitch would triple the efficiency.

The new performance indicative index of filling efficiency enables the package designers to justify the variation effect of underfill parameter on the overall underfill process. Moreover, the upper limit of scaling factor for scaled-up package was derived to serve as the guideline for future scaled-up underfill experiments.

The performance of underfill process as highlighted in this paper was never being quantified before in the past literatures. Similarly, the scaling limit that is associated to the scaled-up underfill experiment was never being reported elsewhere too.

This paper aims to study the filling progression of underfill flow and void formation during the flip-chip encapsulation process.

A new parameter of filling progression that relates volume fraction filled to filling displacement was formulated analytically. Another indicative parameter of filling efficiency was also introduced to quantify the voiding fraction in filling progression. Additionally, the underfill process on different flip-chips based on the past experiments was numerically simulated.

All findings were well-validated with reference to the past experimental results, in terms of quantitative filling progression and qualitative flow profiles. The volume fraction filled increases monotonically with the filling displacement and thus the filling time. As the underfill fluid advances, the size of the void decreases while the filling efficiency increases. Furthermore, the void formed during the underfilling flow stage was caused by the accelerated contact line jump at the bump entrance.

The filling progression enabled manufacturers to forecast the underfill flow front, as it advances through the flip-chip. Moreover, filling progression and filling efficiency could provide quantitative insights for the determination of void formations at any filling stages. The voiding formation mechanism enables the prompt formulation of countermeasures.

Both the filling progression and filling efficiency are new indicative parameters in quantifying the performance of the filling process while considering the reliability defects such as incomplete filling and voiding.

This paper discusses flip chip on FR‐4 and ceramics using non‐conductive adhesive (NCA), anisotropic conductive film (ACF), or anisotropic conductive paste (ACP). Several ACF and ACP materials with different types of adhesive resin and conductive particles and one NCA material were evaluated. Flip chips were assembled on test vehicles for temperature cycling and high‐temperature high‐humidity tests. The reliability performance of the processes was compared. Flip chip processes using NCA, ACF, or ACP could give satisfactory reliability and high assembly yield for some applications, when the bonding parameters were optimised.

Flip chips were assembled on to ceramic boards using eutectic tin‐lead solder with underfill and with/without encapsulation for temperature cycling and high‐temperature‐high‐humidity tests. After 1.5 years of testing, the reliability performance of the flip chip on board (FCOB) assemblies was compared. All of the FCOB assemblies with underfill, but without encapsulation, survived 5,778 cycles of the temperature cycling test following 5,005 hours of the high‐temperature and high‐humidity test. The results show that encapsulation may not necessarily enhance the reliability of flip chip assemblies and might therefore be omitted.

This paper discusses processes of flip chip on FR‐4 using eutectic solder bumps with possible fewer process steps compared to the full assembly process. Some interesting results in terms of the reliability performance of flip chip on FR‐4 assemblies using eutectic solder have been obtained after an almost‐one‐year temperature cycling test. The process steps of underfilling and curing of underfill can be omitted when a suitable epoxy is used for encapsulation. When underfill is conducted, encapsulation is not necessarily needed from a reliability point of view.

Reports the research and development results on flip chip on FR‐4 and ceramics, using anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or eutectic solder with underfill. Several types of ACF and ACP with different types of conductive particles and adhesives were investigated. Simple but high yield procedures for reworking flip chip on board using ACP and ACF were developed. Processes for flip chip on FR‐4 and ceramic boards using eutectic solder bumps with underfill were also evaluated. The flip chips were assembled on test vehicles for temperature cycling and high‐temperature high‐humidity tests. The reliability performance of the three processes (gold bumps with ACF, gold bumps with ACP, and eutectic solder bumps with underfill) is compared.

The purpose of this paper is to study the intermetallic compound (IMC) thickness, composition and morphology in 100-μm pitch and 200-μm pitch Sn–Ag–Cu (SAC305) flip-chip assemblies after bump reflow and assembly reflow. In particular, emphasis is placed on the effect of solder joint size on the interfacial IMCs between metal pads and solder matrix.

This work uses 100-μm pitch and 200-μm pitch silicon flip chips with nickel (Ni) pads and stand-off height of approximately 45 and 90 μm, respectively, assembled on substrates with copper (Cu) pads. The IMCs evolution in solder joints was investigated during reflow by using 100- and 200-μm pitch flip-chip assemblies.

After bump reflow, the joints size controls the IMC composition and dominant IMC type as well as IMC thickness and also influences the dominant IMC morphology. After assembly reflow, the cross-reaction of the pad metallurgies promotes the dominant IMC transformation and shape coarsened on the Ni pad interface for smaller joints and promotes a great number of new dominate IMC growth on the Ni pad interface in larger joints. On the Cu pad interface, many small voids formed in the IMC in larger joints, but were not observed in smaller joints, combined with the drawing of the IMC growth process.

With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 to150 μm. This work shows that as the packaging size reduced with the solder joint interconnection, the solder size becomes an important factor in the intermetallic composition as well as morphology and thickness after reflow.