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The purpose of this paper is to study and discuss the effects of the finite metallisation thickness and conductivity on the properties of microstrip lines.

Effective dielectric constant and attenuation constant of microstrip lines with finite metallization thickness and finite conductivity are analyzed by the method of lines. The experimental results are obtained by using Vector Network Analyzer and the 3680 V Universal Test Fixture of Anritsu.

The strip thickness has a great impact on the attenuation constant of the microstrip lines. The effects can be divided into three parts by the relationship between strip thickness (t) and skindepth (δ). When t<δ, the attenuation constant will decrease rapidly as the strip thickness increase. When δ < t<2δ, the attenuation constant still decrease rapidly as the strip thickness increase, but the slope of the curve will be smaller. When 2δ < t, the effects of the strip thickness will become insignificant and the attenuation constant still decrease slowly as the strip thickness increase.

This paper presents some useful principles about the effects of the finite metallization thickness and finite conductivity in microstrip lines. The reasons for these effects are discussed by analyzing the longitudinal electric field distribution in the strip. Finally, some experimental results are given to verify these principles.

Characterisation and use of dielectric materials with high permittivity are one of the most developed areas of research in microwave circuit simulation. This is mainly because of their various applications in VHF/UHF and microwave frequencies (correlators, instrumentation systems, …). The primary virtue of high‐dielectric substrates for microwave circuits is the reduced size. Since the high dielectric microstrip line also exhibit low loss and useful impedance range, this class of circuits will undoubtedly find wide applications in microwave integrated circuitry.

Owing to the complexity of the electromagnetic problem, numerical methods become an indispensable tool for analysis and modeling of electromagnetic structures. They are the basis to set‐up computer‐aided design (CAD) packages. These models must be accurate, reliable, easily extracted and need limited computational requirements. Since there was a demand for a model able to describe these parameters accurately, an extension of the spectral domain approach (SDA) is proposed for microstrip lines with high permittivity. The analysis is based on the solution of a system of algebraic equations, which are derived from Galerkin's technique in the spectral domain.

Analytical expressions are deduced by curve‐fitting techniques. These expressions can be easily implemented in a CAD simulation tool to design wireless communication components. In this paper, we have developed accurate and suitable general expressions for characteristic parameters for a wide range of ε_r between 1 and 500. The computed results were compared to those available in the literature when possible. In order to validate our models for high values of dielectric constant (128 < ε_r<500), neural models were generated for the characteristic impedance and effective permittivity. A very good agreement is demonstrated.

The originality of this paper consists on the development of design formulas to characterise the microstrip lines with high dielectric constant substrate. Closed form equations are almost non‐existent in the technical literature since the available design formulas have been developed only for dielectric media value ε_r not exceed 128.

The purpose of this paper is to optimize experimental parameters and gain further insights into the plating process in the fabrication of high-density interconnections of printed circuit boards (PCBs) by the rotating disc electrode (RDE) model. Via metallization by copper electrodeposition for interconnection of PCBs has become increasingly important. In this metallization technique, copper is directly filled into the vias using special additives. To investigate electrochemical reaction mechanisms of electrodeposition in aqueous solutions, using experiments on an RDE is common practice.

An electrochemical model is presented to describe the kinetics of copper electrodeposition on an RDE, which builds a bridge between the theoretical and experimental study for non-uniform copper electrodeposition in PCB manufacturing. Comsol Multiphysics, a multiphysics simulation platform, is invited to modeling flow field and potential distribution based on a two-dimensional (2D) axisymmetric physical modeling. The flow pattern in the electrolyte is determined by the 2D Navier–Stokes equations. Primary, secondary and tertiary current distributions are performed by the finite element method of multiphysics coupling.

The ion concentration gradient near the cathode and the thickness of the diffusion layer under different rotating velocities are achieved by the finite element method of multiphysics coupling. The calculated concentration and boundary layer thicknesses agree well with those from the theoretical Levich equation. The effect of fluid flow on the current distribution over the electrode surface is also investigated in this model. The results reveal the impact of flow parameters on the current density distribution and thickness of plating layer, which are most concerned in the production of PCBs.

By RDE electrochemical model, we build a bridge between the theoretical and experimental study for control of uniformity of plating layer by concentration boundary layer in PCB manufacturing. By means of a multiphysics coupling platform, we can accurately analyze and forecast the characteristic of the entire electrochemical system. These results reveal theoretical connections of current density distribution and plating thickness, with controlled parameters in the plating process to further help us comprehensively understand the mechanism of copper electrodeposition.

A large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties.

This paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias).

The fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100  × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out.

This paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.

The solder joint reliability of FC components on organic substrates is questionable unless underfill is used to relieve the thermal strains. Besides the mechanical protection, underfill provides the solder and I.C. surface with protection against the environment. Underfilling is however, time‐consuming and expensive. In an electrical sense, the underfill has no beneficial function and should, therefore, be considered as a ballast in an electronic assembly. However, to obtain a satisfactory level of reliability without underfill some novel methods are required. Wafer thinning is often performed to fit a die into a thin package, e.g. in smart cards. In this paper, the issue of thinning a package is studied utilizing 3D finite element method models. Various die and board thicknesses are evaluated with respect to their effect on the reliability of FC solder bumps. In addition, a novel idea to increase the joint reliability is studied.

A new hybrid substrate technology for power electronic applications has been characterised by thermal resistance and mechanical stress measurements. The new substrate utilises thermal spray technology for deposition of dielectric layer and electrical conductors. The results are compared with the more established technology of alumina substrates with direct copper bonding (DCB) metallisation. Silicon test chips for thermal resistance and mechanical stress measurement were used for the characterisation. The experimental results were compared with finite element analysis and a reasonable agreement was found.

The purpose of this paper is to present a new multilayer process for three‐dimensional molded interconnect devices (3D‐MIDs) that allows the assembly of modern area array packaged semiconductors.

A new 3D‐MID multilayer process based on local overmolding is developed. To investigate this new process, a 3D demonstrator is designed, simulated and fabricated. Various technologies such as injection molding, maskless laser assisted electroless metallization, overmolding and laser via drilling are used.

Using the new 3D‐MID multilayer process a 3D demonstrator with three metallization layers is fabricated. Injection molding simulation is utilized to ensure a feasible demonstrator design. It is shown that a surface laser treatment improves layer‐to‐layer adhesion during the process. Shear and pull tests prove the adhesion promotion. The 3D fine‐pitch‐metallization is done down to 60 μm track width. Via resistance is measured by four terminal sensing in agreement with previous results. Design rules for process compatible vias are introduced. The fabricated demonstrator is suitable for flip‐chip‐based area array packaged semiconductors.

A proof of concept is given by the fabricated demonstrator. Further, work should include reliability tests of the multilayer structures and improvement of individual process steps.

The paper describes a new multilayer process for 3D‐MIDs. It overcomes existing restrictions regarding the electrical routing on 3D‐MID surfaces. The compatibility of area array packaged semiconductors with a high‐inputs/outputs count and the 3D‐MID technology is improved.

This paper aims to present new technological approaches of manufacturing of micromechanical gyroscope ring-sensitive element based on the nanoporous anodic alumina instead of traditional silicon technology. Simulation and the operation analyses of such elements have been performed.

The design of gyroscope represents a sensitive element on a glass substrate; in the center of a ring, there is a permanent magnet in a steel box. The sensitive element is made of profiled nanoporous anodic alumina consisting of an octagonal frame which is connected to a ring in the center with eight N-shaped spokes. The technology of the sensitive element fabrication involves the electrochemical formation of nanoporous anodic alumina substrate given the thickness and porosity and its chemical etching on the element topology. The basic parameters and the operation principle of the nanoporous alumina-sensitive element have been defined by finite element simulation.

It is shown that the resonance frequencies of the sensitive element change as functions of the alumina porosity. The main parameters of the nanoporous alumina-sensitive element have been compared with parameters of a silicon-sensitive element. Calculations have shown that the mechanical deformations of the von Mises are approximately lower by two times in the nanoporous alumina-sensitive element.

High-precision angular rate measurement will be achieved by reducing mechanical and electrical noises practically to zero through careful designing of a ring magnetoelectric gyroscope

The ring resonator made of nanoporous anodic alumina will allow to increase the threshold of sensitivity and stability of micromechanical gyroscope characteristics owing to the high precision of geometric dimensions, the stability of the elastic properties and the quality factor.

Because of the need for electronics use at temperatures beyond 150°C, high temperature resistant interconnection technologies like transient liquid phase (TLP) soldering and silver sintering are being developed which are not only replacements of high-lead solders, but also open new opportunities in terms of temperature resistance and reliability. The paper aims to address the thermo-mechanical reliability issues that have to be considered if the new interconnection technologies will be applied.

A TLP soldering technique is briefly introduced and new challenges concerning the thermo-mechanical reliability of power devices are worked out by numerical analysis (finite element simulation). They arise as the material properties of the interconnect materials differ substantially from those known for soft solders. The effective material responses of the new materials are determined by localized unit cell models that capture the inhomogeneous structure of the materials.

It is shown that both the TLP solder layer and the Ag-sinter layer have much less ductility and show less creep than conventional soft solders. The potential failure modes of an assembly made by TLP soldering or Ag sintering change. In particular, the characteristic low cycle fatigue solder failures become unlikely and are replaced either by metallization fatigue, brittle failure of intermetallic compound, components, or interfaces.

A variety of new failure risks, which have been analyzed theoretically, can be avoided only if they are known to the potential user of the new techniques. It is shown that an optimal reliability will be strongly dependent on the actual assembly design.

Fast laser soldering processes are very attractive for the production of miniaturized interconnections with high reliability as they allow solder joint quality assurance during soldering. In order to evaluate the solder joint quality temporal changes of the temperature distribution inside the solder joint due to melting of the solder and wetting of the component and the pad metallizations must be well understood. In this paper we present thermal simulations of fast laser soldering processes taking the essential changes of the solder geometry into account. Moreover, we use a new relation for the calculation of the moment of wetting in dependence of the interface temperature. With this model the influence of the wettability of the pad and the component metallization and of the position of the laser beam on the temperature distribution inside the solder joint are investigated.