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Variable fractional delay filtering is an important technology in signal processing; the research shows that all-pass variable fractional delay (VFD) filters achieve higher design accuracy than FIR VFD filters; therefore, the design, analysis and implementation of all-pass VFD filters are of great importance.

In this paper, a two-stage approach for the design of general 1-D stable VFD all-pass filters is proposed. The method takes the desired group delay range [N−1, N], where N is the filter order.

The design algorithm is decomposed into two design stages: first, a set of fixed delay all-pass filters are designed by minimizing a set of objective functions defined in terms of approximating error criterion and filter stability constraint. Then, the design result is determined by fitting each of the fixed delay all-pass filter coefficients as 1-D polynomials. A design example together with its comparisons with those of the recent literature studies is given to justify the effectiveness of the proposed design method.

An illustrating design example shows that the method proposed can achieve better filter performances than the existing ones.

The purpose of the paper is to present a novel design method for the optimal finite word length (FWL) finite impulse response (FIR) filters.

The design method is based on a parallel tabu search (TS) algorithm which uses the crossover operator of the genetic algorithm.

Three design examples have been presented to show that the proposed method can provide a good solution to the design problem of a FWL FIR filter. In order to show the validity of the proposed method, the performance of the suggested method has been compared to those of widely‐used other methods. From the comparison results, it was concluded that the proposed method can be efficiently used for the optimal FWL FIR filter design.

The number of examples can be increased and also the performance of the proposed method might be compared to other design methods, apart from those presented in this work, developed for the design of optimal FWL FIR filters.

The use of this method produces optimal digital FWL FIR filters with low complexity and therefore provides advantages in the terms of speed and cost.

The originality is the application of the parallel TS algorithm described by the authors to the FWL FIR filter design. The work presented in the paper is particularly important for the researchers studying on the design methods for FWL FIR filter design and the applications of these type filters.

Filter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters. Designing filters with lower complexity, minimized area and enhanced speed is a demanding task in currently prevailing communication standards. This study aims to propose an efficient reconfigurable residue number system (RNS)-based multiply-accumulate (MAC) channel filter for software radio receivers.

RNS-based pipelined MAC module for the realization of channel finite impulse response (FIR) filter architecture is considered in this work. Further, the use of a single adder and single multiplier for realizing the filter architecture regardless of the number of taps offers effective resource sharing. This design provides significant improvement in speed of operation as well as a reduction in area complexity.

In this paper, two major tasks have been considered: first, the RNS number conversion is performed in which the integer is converted into several residues. These residues are processed in parallel and are applied to the MAC-FIR filter architecture. Second, the MAC filter architecture involves pipelining, which enhances the speed of operation to a significant extent. Also, the time-sharing-based design incorporates a single partial product-based shift and add multiplier and single adder, which provide a low complex design. The results show that the proposed 16-tap RNS-based pipelined MAC sub-filter achieves significant improvement in speed as well as 89.87% area optimization when examined with the conventional RNS-based FIR filter structure.

The proposed MAC-FIR filter architecture provides good performance in terms of complexity and speed of operation because of the use of the RNS scheme with pipelining and partial product-based shift and adds multiplier and single adder when examining with the conventional designs. The reported architecture can be used in software radios.

Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.

The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

The digital down converter (DDC) is a principal component in modern communication systems. The DDC process traditionally entails quadrature down conversion, bandwidth reducing filters and commensurate sample rate reduction. To avoid group delay, distortion linear phase FIR filters are used in the DDC. The filter performance specifications related to deep stopband attenuation, small in-band ripple and narrow transition bandwidth lead to filters with a large number of coefficients. To reduce the computational workload of the filtering process, filtering is often performed as a two-stage process, the first stage being a down sampling Hoegenauer (or cascade-integrated comb) filter and a reduced sample rate FIR filter. An alternative option is an M-Path polyphase partition of a band cantered FIR filter. Even though IIR filters offer reduced workload to implement a specific filtering task, the authors avoid using them because of their poor group delay characteristics. This paper aims to propose the design of M-path, approximately linear phase IIR filters as an alternative option to the M-path FIR filter.

Two filter designs are presented in the paper. The first approach uses linear phase IIR low pass structure to reduce the filter’s coefficient. Whereas the second approach uses multipath polyphase structure to design approximately linear phase IIR filter in DDC.

The authors have compared the performance and workload of the proposed polyphase structured IIR filters with state-of-the-art filter design used in DDC. The proposed design is seen to satisfy tight design specification with a significant reduction in arithmetic operations and required power consumption.

The proposed design is an alternate solution to the M-path polyphase FIR filter offering very less number of coefficients in the filter design. Proposed DDC using polyphase structured IIR filter satisfies the requirement of linear phase with the least number of computation cost in comparison with other DDC structure.

In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.

The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.

Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.

The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

This paper aims to present the design of a novel triangular-shaped wideband microstrip bandpass filter implemented on a low-cost substrate with a notched band for interference rejection.

The conventional dual-stub filter is embedded with simple fractal-based triangular-circular geometries through various iterations to reject wireless local area network (WLAN) signals with a notched band at 5.8 GHz.

The filter covers a wide frequency band from 3.1 to 8.8 GHz and has a fractional bandwidth of 98 per cent with the lower passband of 57.5 per cent and upper passband of 31.6 per cent separated by a notched band at 5.8 GHz. The proposed wideband prototype bandpass filter is fabricated in FR-4 substrate using PCB technology and the simulation results are validated with measurement results which include insertion loss, return loss and group delay. The fabricated filter has a sharp rejection of 28.3 dB at 5.8 GHz. Measured results show good agreement with simulated responses. The performance of the fractal-based wideband filter is compared with other wideband bandpass filters.

In the proposed work, a fractal-based wideband bandpass filter with a notched band is reported. The conventional dual-stub filter is deployed with triangular-circular geometry to design a wideband filter with a notched band to suppress interference signals at WLAN frequency. The proposed wideband filter exhibits smaller size and better interference rejection compared to other wideband bandpass filter designs implemented on low-cost substrate reported in the literature. The aforementioned wideband filter finds application in wideband wireless communication systems.

This paper aims to concentrate on an efficient finite impulse response (FIR) filter architecture in combination with the differential evolution ant colony algorithm (DE-ACO). For the design of FIR filter, the evolutionary algorithm (EA) is found to be very efficient because of its non-conventional, nonlinear, multi-modal and non-differentiable nature. While focusing with frequency domain specifications, most of the EA techniques described with the existing systems diverge from the power related matters.

The FIR filters are extensively used for many low power, low complexities, less area and high speed digital signal processing applications. In the existing systems, various FIR filters have been proposed to focus on the above criterion.

In the proposed method, a novel DE-ACO is used to design the FIR filter. It focuses on satisfying the economic power utilization and also the specifications in the frequency domain.

The proposed DE-ACO gives outstanding performance with a strong ability to find optimal solution, and it has got quick convergence speed. The proposed method also uses the Software integrated synthesis environment (ISE) project navigator (p.28xd) for the simulation of FIR filter based on DE-ACO techniques.

Traditionally, each time a new design for a finite impulse response (FIR) filter is required, a new algorithm has to be developed specially for the FIR filter. Furthermore, corresponding hardware architecture must be designed specially to meet the requirement of the FIR specifications. The purpose of this paper is to propose an arithmetic logic unit (ALU)‐based universal FIR filter suitable for realization in field programmable gate arrays (FPGA), where various FIR filters can be implemented just by programming instructions in the ROM with identical hardware architecture.

Rather than multiplier‐accumulator‐based architecture for conventional FIR, the proposed ALU architecture implements the FIR functions by using accumulators and shift‐registers controlled by the instructions of ROM. Furthermore, time division multiplexing access (TDMA) technique is employed to reduce the chip size. In addition, the proposed FIR architecture is verified in a SOC hardware and/or software co‐emulation system.

An ALU‐based universal FIR filter suitable for realization in FPGA is designed and verified in a SOC hardware/software co‐emulation system with example of a 64‐tap FIR filter design.

A software‐based design method as well as TDMA scheme for the ALU‐based FIR filter are introduced, making FIR filter architecture universal, programmable, and consuming less FPGA resources.

This paper aims to achieve two main objectives. First, to introduce to the literature a new versatile active building block, namely, voltage differencing differential voltage current conveyor (VD-DVCC) for analog signal processing applications. Second, to design a novel electronically tunable mixed-mode universal filter. The designed filter provides low-pass, high-pass, band-pass, band-reject and all-pass responses in voltage-mode (VM), current-mode (CM), trans-impedance-mode (TIM) and trans-admittance-mode (TAM).

The proposed filter uses two VD-DVCCs, three resistors and two capacitors. All the capacitors used are grounded, which is advantageous from the monolithic integration point of view. The VD-DVCC is designed and validated in Cadence software using CMOS 0.18 µm process design kit from Silterra Malaysia at a supply voltage of ±1 V.

The proposed novel filter enjoys many attractive features including as follows: the ability to operate in all four modes, no requirement of capacitive matching, tunability of quality factor (Q) independent of pole frequency, availability of both inverting and non-inverting outputs for VM and TIM mode, high output impedance explicit current output for CM and TAM, no requirement for double/negative input signals (voltage/current) for response realization and low active and passive sensitivities. The filter is designed for a pole frequency of 5.305 MHz. The obtained results bear a close resemblance with the theoretical findings.

The proposed novel filter structure requires a minimum number of active and passive components and provides operation in all four operating modes. The filter will find application in structures of mixed-mode systems.