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This study aims to investigate the thermal fracture mechanism of moisture-preconditioned SAC305 ball grid array (BGA) solder joints subjected to multiple reflow and thermal cycling.

The BGA package samples are subjected to JEDEC Level 1 accelerated moisture treatment (85 °C/85%RH/168 h) with five times reflow at 270 °C. This is followed by multiple thermal cycling from 0 °C to 100 °C for 40 min per cycle, per IPC-7351B standards. For fracture investigation, the cross-sections of the samples are examined and analysed using the dye-and-pry technique and backscattered scanning electron microscopy. The packages' microstructures are characterized using an energy-dispersive X-ray spectroscopy approach. Also, the package assembly is investigated using the Darveaux numerical simulation method.

The study found that critical strain density is exhibited at the component pad/solder interface of the solder joint located at the most distant point from the axes of symmetry of the package assembly. The fracture mechanism is a crack fracture formed at the solder's exterior edges and grows across the joint's transverse section. It was established that Au content in the formed intermetallic compound greatly impacts fracture growth in the solder joint interface, with a composition above 5 Wt.% Au regarded as an unsafe level for reliability. The elongation of the crack is aided by the brittle nature of the Au-Sn interface through which the crack propagates. It is inferred that refining the solder matrix elemental compound can strengthen and improve the reliability of solder joints.

Inspection lead time and additional manufacturing expenses spent on investigating reliability issues in BGA solder joints can be reduced using the study's findings on understanding the solder joint fracture mechanism.

Limited studies exist on the thermal fracture mechanism of moisture-preconditioned BGA solder joints exposed to both multiple reflow and thermal cycling. This study applied both numerical and experimental techniques to examine the reliability issue.

This study aims to investigate the possible defects and their root causes in a soft-termination multilayered ceramic capacitor (MLCC) when subjected to a thermal reflow process.

Specimens of the capacitor assembly were subjected to JEDEC level 1 preconditioning (85 °C/85%RH/168 h) with 5× reflow at 270°C peak temperature. Then, they were inspected using a 2 µm scanning electron microscope to investigate the evidence of defects. The reliability test was also numerically simulated and analyzed using the extended finite element method implemented in ABAQUS.

Excellent agreements were observed between the SEM inspections and the simulation results. The findings showed evidence of discontinuities along the Cu and the Cu-epoxy layers and interfacial delamination crack at the Cu/Cu-epoxy interface. The possible root causes are thermal mismatch between the Cu and Cu-epoxy layers, moisture contamination and weak Cu/Cu-epoxy interface. The maximum crack length observed in the experimentally reflowed capacitor was measured as 75 µm, a 2.59% difference compared to the numerical prediction of 77.2 µm.

This work's contribution is expected to reduce the additional manufacturing cost and lead time in investigating reliability issues in MLCCs.

Despite the significant number of works on the reliability assessment of surface mount capacitors, work on crack growth in soft-termination MLCC is limited. Also, the combined experimental and numerical investigation of reflow-induced reliability issues in soft-termination MLCC is limited. These cited gaps are the novelties of this study.

This study aims to investigate the reliability issues of microvoid cracks in solder joint packages exposed to thermal cycling fatigue.

The specimens are subjected to JEDEC preconditioning level 1 (85 °C/85%RH/168 h) with five times reflow at 270°C. This is followed by thermal cycling from 0°C to 100°C, per IPC-7351B standards. The specimens' cross-sections are inspected for crack growth and propagation under backscattered scanning electronic microscopy. The decoupled thermomechanical simulation technique is applied to investigate the thermal fatigue behavior. The impacts of crack length on the stress and fatigue behavior of the package are investigated.

Cracks are initiated from the ball grid array corner of the solder joint, propagating through the transverse section of the solder ball. The crack growth increases continuously up to 0.25-mm crack length, then slows down afterward. The J-integral and stress intensity factor (SIF) values at the crack tip decrease with increased crack length. Before 0.15-mm crack length, J-integral and SIF reduce slightly with crack length and are comparatively higher, resulting in a rapid increase in crack mouth opening displacement (CMOD). Beyond 0.25-mm crack length, the values significantly decline, that there is not much possibility of crack growth, resulting in a negligible change in CMOD value. This explains the crack growth arrest obtained after 0.25-mm crack length.

This work's contribution is expected to reduce the additional manufacturing cost and lead time incurred in investigating reliability issues in solder joints.

The work investigates crack propagation mechanisms of microvoid cracks in solder joints exposed to moisture and thermal fatigue, which is still limited in the literature. The parametric variation of the crack length on stress and fatigue characteristics of solder joints, which has never been conducted, is also studied.

This paper aims to investigate the effect of physical vapor deposition (PVD)-coated stencil wall aperture on the life span of fine-pitch stencil printing.

The fine-pitch stencil used in this work is fabricated by electroform process and subsequently nano-coated using the PVD process. Stencil printing process was then performed to print the solder paste onto the printed circuit board (PCB) pad. The solder paste release was observed by solder paste inspection (SPI) and analyzed qualitatively and quantitatively. The printing cycle of up to 80,000 cycles was used to investigate the life span of stencil printing.

The finding shows that the performance of stencil printing in terms of solder printing quality is highly dependent on the surface roughness of the stencil aperture. PVD-coated stencil aperture can prolong the life span of stencil printing with an acceptable performance rate of about 60%.

Stencil printing is one of the important processes in surface mount technology to apply solder paste on the PCB. The stencil’s life span greatly depends on the type of solder paste, stencil printing cycles involved and stencil conditions such as the shape of the aperture, size and thickness of the stencil. This study will provide valuable insight into the relationship between the coated stencil wall aperture via PVD process on the life span of fine-pitch stencil printing.

This study aims to investigate crack propagation in a moisture-preconditioned soft-termination multi-layer ceramic capacitor (MLCC) during thermal reflow process.

Experimental and extended finite element method (X-FEM) numerical analyses were used to analyse the soft-termination MLCC during thermal reflow. A cross-sectional field emission scanning electron microscope image of an actual MLCC’s crack was used to validate the accuracy of the simulation results generated in the study.

At 270°C, micro-voids between the copper-electrode and copper-epoxy layers absorbed 284.2 mm/mg³ of moisture, which generated 6.29 MPa of vapour pressure and caused a crack to propagate. Moisture that rapidly vaporises during reflow can cause stresses that exceed the adhesive/substrate interface’s adhesion strength of 6 MPa. Higher vapour pressure reduces crack development resistance. Thus, the maximum crack propagation between the copper-electrode and copper-epoxy layers at high reflow temperature was 0.077 mm. The numerical model was well-validated, as the maximum crack propagation discrepancy was 2.6%.

This research holds significant implications for the industry by providing valuable insights into the moisture-induced crack propagation mechanisms in soft-termination MLCCs during the reflow process. The findings can be used to optimise the design, manufacturing and assembly processes, ultimately leading to enhanced product quality, improved performance and increased reliability in various electronic applications. Moreover, while the study focused on a specific type of soft-termination MLCC in the reflow process, the methodologies and principles used in this research can be extended to other types of MLCC packages. The fundamental understanding gained from this study can be extrapolated to similar structures, enabling manufacturers to implement effective strategies for crack reduction across a wider range of MLCC applications.

The moisture-induced crack propagation in the soft-termination MLCC during thermal reflow process has not been reported to date. X-FEM numerical analysis on crack propagation have never been researched on the soft-termination MLCC.

This paper aims to study the interfacial delamination found in the boundary of the copper/copper-epoxy layers of a multi-layer ceramic capacitor.

The thermal reflow process of the capacitor assembly and the crack propagation from the initial micro voids presented in the boundary, and later manifested into delamination, were numerically simulated. Besides, the cross section of the capacitor assembly was inspected for delamination cracks and voids using a scanning electronic microscope.

Interfacial delamination in the boundary of copper/copper-epoxy layers was caused by the thermal mismatch and growth of micro voids during the thermal reflow process. The maximum deformation on the capacitor during reflow was 2.370 µm. It was found that a larger void would induce higher vicinity stress, mode I stress intensity factor, and crack elongation rate. Moreover, the crack extension increased with the exerted deformation until 0.3 µm, before saturating at the peak crack extension of around 0.078 µm.

The root cause of interfacial delamination issues in capacitors due to thermal reflow has been identified, and viable solutions proposed. These can eliminate the additional manufacturing cost and lead time incurred in identifying and tackling the issues; as well as benefit end-users, by promoting the electronic device reliability and performance.

To the best of the authors’ knowledge, the mechanism of delamination occurrence in a capacitor during has not been reported to date. The parametric variation analysis of the void size and deformation on the crack growth has never been conducted.