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1 – 10 of 275Czeslaw T. Kowalski and Jacek D. Lis
The purpose of this paper is to present a fixed‐point implementation of a complete direct torque control (DTC) algorithm connected with a rotor speed estimation algorithm for the…
Abstract
Purpose
The purpose of this paper is to present a fixed‐point implementation of a complete direct torque control (DTC) algorithm connected with a rotor speed estimation algorithm for the induction motor drive, using field‐programmable gate array (FPGA).
Design/methodology/approach
The parallel processing approach is described, which requires a decomposition of the control and estimation algorithms for the converter‐fed induction motor to several tasks, realised in parallel. The advanced data processing techniques are described, like PIPELINE technique for data streams design, coordinate rotation digital computer algorithm for transformation of stator flux vector components from Cartesian to polar coordinates. Moreover, the method for the qualitative analysis of the full‐order state observer's sensitivity to the variations of the induction motor equivalent circuit parameters is presented.
Findings
It is shown that the developed FPGA‐based DTC structure enables designing an efficient application for the induction motor control. Owing to the high‐processing frequency, the digital FPGA‐based DTC application is similar in its features to the analogue realisation based on the comparators. Yet all the advantages of the digital structure, i.e. high flexibility, parameterization capability, etc. remain unchanged. Furthermore, FPGA is hardware realisation of a digital data processing algorithm; hence the reliability of the control system is improved.
Research limitations/implications
The investigations are performed in the developing prototype setup, based on PXI‐1042 Industrial PC equipped with Xilinx Virtex‐II FPGA matrix, programmed with LabVIEW.
Practical implications
The experimental tests of the FPGA‐based implementation of the whole control structure of the sensorless DTC drive system are demonstrated. It is also shown, that the full‐order state observer with the speed adaptation loop is significantly sensitive to motor parameter variations in the low‐speed region, which must be taken into account while designing the adaptation algorithm for speed estimation in real application.
Originality/value
The paper's value lies in the overall, FPGA‐based design of the speed sensorless DTC structure for the induction motor including motor speed, torque and stator flux control loops, stator flux and rotor speed estimation.
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Keywords
Hiren K. Mewada, Jitendra Chaudhari, Amit V. Patel, Keyur Mahant and Alpesh Vala
Synthetic aperture radar (SAR) imaging is the most computational intensive algorithm and this makes its implementation challenging for real-time application. This paper aims to…
Abstract
Purpose
Synthetic aperture radar (SAR) imaging is the most computational intensive algorithm and this makes its implementation challenging for real-time application. This paper aims to present the chirp-scaling algorithm (CSA) for real-time SAR applications, using advanced field programmable gate array (FPGA) processor.
Design/methodology/approach
A chirp signal is generated and compressed using range Doppler algorithm in MATAB for validation. Fast Fourier transform (FFT) and multiplication operations with complex data types are the major units requiring heavy computation. Therefore, hardware acceleration is proposed and implemented on NEON-FPGA processor using NE10 and CEPHES library.
Findings
The heuristic analysis of the algorithm using timing analysis and resource usage is presented. It has been observed that FFT execution time is reduced by 61% by boosting the performance of the algorithm and speed of multiplication operation has been doubled because of the optimization.
Originality/value
Very few literatures have presented the FPGA-based SAR imaging implementation, where analysis of windowing technique was a major interest. This is a unique approach to implement the SAR CSA using a hybrid approach of hardware–software integration on Zynq FPGA. The timing analysis propagates that it is suitable to use this model for real-time SAR applications.
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Jai Gopal Pandey, Sanskriti Gupta and Abhijit Karmakar
The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The…
Abstract
Purpose
The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.
Design/methodology/approach
An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.
Findings
FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.
Originality/value
The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.
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Keywords
Yunfei Li, Shengbo Eben Li, Xingheng Jia, Shulin Zeng and Yu Wang
The purpose of this paper is to reduce the difficulty of model predictive control (MPC) deployment on FPGA so that researchers can make better use of FPGA technology for academic…
Abstract
Purpose
The purpose of this paper is to reduce the difficulty of model predictive control (MPC) deployment on FPGA so that researchers can make better use of FPGA technology for academic research.
Design/methodology/approach
In this paper, the MPC algorithm is written into FPGA by combining hardware with software. Experiments have verified this method.
Findings
This paper implements a ZYNQ-based design method, which could significantly reduce the difficulty of development. The comparison with the CPU solution results proves that FPGA has a significant acceleration effect on the solution of MPC through the method.
Research limitations implications
Due to the limitation of practical conditions, this paper cannot carry out a hardware-in-the-loop experiment for the time being, instead of an open-loop experiment.
Originality value
This paper proposes a new design method to deploy the MPC algorithm to the FPGA, reducing the development difficulty of the algorithm implementation on FPGA. It greatly facilitates researchers in the field of autonomous driving to carry out FPGA algorithm hardware acceleration research.
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Dong Zhu, Liping Hou, Mo Chen and Bocheng Bao
The purpose of this paper is to develop an field programmable gate array (FPGA)-based neuron circuit to mimic dynamical behaviors of tabu learning neuron model.
Abstract
Purpose
The purpose of this paper is to develop an field programmable gate array (FPGA)-based neuron circuit to mimic dynamical behaviors of tabu learning neuron model.
Design/methodology/approach
Numerical investigations for the tabu learning neuron model show the coexisting behaviors of bi-stability. To reproduce the numerical results by hardware experiments, a digitally FPGA-based neuron circuit is constructed by pure floating-point operations to guarantee high computational accuracy. Based on the common floating-point operators provided by Xilinx Vivado software, the specific functions used in the neuron model are designed in hardware description language programs. Thus, by using the fourth-order Runge-Kutta algorithm and loading the specific functions orderly, the tabu learning neuron model is implemented on the Xilinx FPGA board.
Findings
With the variation of the activation gradient, the initial-related coexisting attractors with bi-stability are found in the tabu learning neuron model, which are experimentally demonstrated by a digitally FPGA-based neuron circuit.
Originality/value
Without any piecewise linear approximations, a digitally FPGA-based neuron circuit is implemented using pure floating-point operations, from which the initial conditions-related coexisting behaviors are experimentally demonstrated in the tabu learning neuron model.
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Neeraj Bisht, Bishwajeet Pandey and Sandeep Kumar Budhani
Privacy and security of personal data is the prime concern in any communication. Security algorithms play a crucial role in privacy preserving and are used extensively. Therefore…
Abstract
Purpose
Privacy and security of personal data is the prime concern in any communication. Security algorithms play a crucial role in privacy preserving and are used extensively. Therefore, these algorithms need to be effective as well as energy-efficient. Advanced Encryption Standards (AES) is one of the efficient security algorithms. The principal purpose of this research is to design Energy efficient implementation of AES, as it is one of the important aspects for a step toward green computing.
Design/methodology/approach
This paper presents a low voltage complementary metal oxide semiconductor (LVCMOS) based energy efficient architecture for AES encryption algorithm on Field Programmable Gate Array (FPGA) platform. The experiments are performed for five different FPGAs at different input/output standards of LVCMOS. Experiments are performed separately at two frequencies (default and 1.6 GHz).
Findings
The comparative study of total on-chip power consumption for different frequency suggested that LVCMOS12 performed best for all the FPGAs. Also, Kintex-7 Low Voltage was found to be the best performing FPGA. At 1.6 GHz frequency, the authors observed 55% less on-chip power consumption when switched from Artix-7 with LVCMOS33 (maximum power consuming combination) to Kintex-7 Low Voltage with LVCMOS12. Mathematical models are developed for the proposed design.
Originality/value
The green implementation of AES algorithm based on LVCMOS standards has not been explored yet by researchers. The energy efficient implementation of AES will certainly be beneficial for society as it will consume less power and dissipate lesser heat to environment.
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With the rapid development in wired and wireless networks, the demand for network security system is rising rapidly due to more and more new applications introduced. The main…
Abstract
Purpose
With the rapid development in wired and wireless networks, the demand for network security system is rising rapidly due to more and more new applications introduced. The main factors that rate the encryption algorithms are its ability to secure and protect data against attacks, its speed and efficiency. In this paper, a reconfigurable network security design using multi-mode data encryption standard (DES) algorithm has been implemented with low complexity and low cost, which will also reduce the speed. The paper aims to discuss these issues.
Design/methodology/approach
The design can be easily reconfigured to 3DES (triple DES) which is more secure and more powerful in encryption and decryption, as one of the trick in designing 3DES is to reuse three instances of DES. The design can be used for wired and wireless network applications, and it has been described using VHDL and implemented in a reconfigurable Programmable System-on-Chip (PSoC). The hardware implementation has targeted Xilinx Spartan XC3S700-AN FPGA device.
Findings
The main idea of reducing the complexity for the hardware implementation is by optimizing the number of logic gates and LUTs of the design. The number of logic gates can be decreased by changing the way of writing the VHDL code and by optimizing the size of the chip.
Originality/value
The design has been tested in simulation and hardware levels, and the simulation results and performance are discussed.
Details
Keywords
Ying-Shieh Kung, Seng-Chi Chen, Jin-Mu Lin and Tsung-Chun Tseng
The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the…
Abstract
Purpose
The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the slip speed estimator, the space vector pulse width modulation scheme, the quadrature encoder pulse, and analog to digital converter interface circuit, etc. into one field programmable gate array (FPGA).
Design/methodology/approach
First, the mathematical modeling of an IM drive, the field-oriented control algorithm, and PI controller are derived. Second, the very high speed IC hardware description language (VHDL) is adopted to describe the behavior of the algorithms above. Third, based on electronic design automation simulator link, a co-simulation work constructed by ModelSim and Simulink is applied to verify the proposed VHDL code for the speed controller intellectual properties (IP). Finally, the developed VHDL code will be downloaded to the FPGA for further control the IM drive.
Findings
In realization aspect, it only needs 5,590 LEs, 196,608 RAM bits, and 14 embedded 9-bit multipliers in FPGA to build up a speed control IP. In computational power aspect, the operation time to complete the computation of the PI controller, the slip speed estimator, the current vector controller are only 0.28 μs, 0.72 μs, and 0.96 μs, respectively.
Practical implications
Fast computation in FPGA can speed up the speed response of IM drive system to increase the running performance.
Originality/value
This is the first time to realize all the function of a speed controller for IM drive within one FPGA.
Details
Keywords
Abdellah Ferdjali, Momir Stanković, Stojadin Manojlović, Rafal Madonski, Dimitrije Bujaković and Abderraouf Djenadbia
A laser seeker is an important element in missile guidance and control systems, responsible for target detection and tracking. Its control is, however, a challenging problem due…
Abstract
Purpose
A laser seeker is an important element in missile guidance and control systems, responsible for target detection and tracking. Its control is, however, a challenging problem due to complex dynamics and various acting disturbances. Hence, the purpose of this study is to propose a systematic design, tuning, analysis and performance verification of a nonlinear active disturbance rejection control (ADRC) algorithm for the specific case of the laser seeker system.
Design/methodology/approach
The proposed systematic approach of nonlinear ADRC application to the laser seeker system consists of the following steps. The complex laser seeker control problem is first expressed as a regulation problem. Then, a nonlinear extended state observer (ESO) with varying gains is used to improve the performance of a conventionally used linear ESO (LESO), which enables better control quality in both transient and steady-state periods. In the next step, a systematic observer tuning, based on a detailed analysis of the system disturbances, is proposed. The stability of the overall control system is then verified using a describing function method. Next, the implementation of the NESO-based ADRC solution is realized in a fixed-point format using MATLAB/Simulink and Xilinx System Generator. Finally, the considered laser seeker control system is implemented in discrete form and comprehensively tested through hardware-in-the-loop (HIL) co-simulation.
Findings
Through the conducted comparative study of LESO-based and NESO-based ADRC algorithms for the laser seeker system, the advantages of the proposed nonlinear scheme are shown. It is concluded that the NESO-based ADRC scheme for the laser seeker system (with appropriate parameters tuning methodology) provides better control performance in both transient and steady-state periods. The conducted multicriteria study validates the efficacy of the proposed systematic approach of applying nonlinear ADRC to laser seeker systems.
Practical implications
In practice, the obtained results imply that the laser seeker system, governed by the studied nonlinear version of the ADRC algorithm, could potentially detect and track targets faster and more accurately than the system based on the common linear ADRC algorithm. In addition, the article presents the step-by-step procedure for the design, field programmable gate array (FPGA) implementation and HIL-based co-simulation of the proposed nonlinear controller, which can be used by control practitioners as one of the last validation stages before experimental tests on a real guidance system.
Originality/value
The main contribution of this work is the systematic procedure of applying the ADRC scheme with NESO for the specific case of the laser seeker system. It includes its design, tuning, analysis and performance verification (with simulation and FPGA hardware). The novelty of the work is also the combination and practical realization of known theoretical elements (NESO structure, NESO parameter tuning, ADRC closed-loop stability analysis) in the specific case of the laser seeker system. The results of the conducted applied research increase the current state of the art related to robust control of laser seeker systems working in disturbed and uncertain conditions.
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Bishwajeet Pandey, Geetam Singh Tomar, Robin Singh Bhadoria, Dil Muhammad Akbar Hussain and Ciro Rodriguez Rodriguez
The Purpose of this research is to make an energy efficient finite state machine (FSM) in order to achieve the core objective of green computing because FSM is an indispensable…
Abstract
Purpose
The Purpose of this research is to make an energy efficient finite state machine (FSM) in order to achieve the core objective of green computing because FSM is an indispensable part of multiple computer hardware.
Design/methodology/approach
This study uses ultra-scale plus FPGA architecture in place of seven-series field-programmable gate array (FPGA) for the implementation of the FSM design and also uses output load scaling for the design of environment-friendly FSM. This design study is done using Verilog Hardware description language and Vivado integrated system environment design tools and implemented on 16 nm ultra-scale FPGA architecture.
Findings
There is up to 98.57% reduction in dynamic power when operating frequency is managed as per smart job scheduling. There is up to a 21.97% reduction in static power with proper management of output load capacitance. There is up to 98.43% saving in dynamic power with the proposed management of output load capacitance.
Originality/value
The proposed design will be environment friendly that eventually leads to the green earth. This is the main motive of the research area i.e. green computing.
Details