Search results

The purpose of the paper is to investigate photochemical machining characteristics of stainless steel (AISI 304-SS304) parts with a novel design are investigated experimentally from the aspect of process parameters. The effects of phototool pattern geometry, ultraviole (UV) exposure time and etching time on of AISI 304 were evaluated.

The designed semi-automated photochemical manufacturing (PCM) equipment consists of 4 units, which include UV exposure, etching, developing and surface cleaning units. Experimental procedure has been designed via Taguchi method. Results were evaluated via Analysis of Variance (ANOVA) method.

Etching time is the most effective factor in PCM quality of AISI 304 stainless steel. Surface roughness is sensitive to geometrical pattern of the phototool for PCM of AISI 304 UV exposure time is less influential on the PCM quality for stainless steel.

The designed PCM equipment prototype is not fully automated, which requires automation for part replacements into units. The effects of the temperature inside chemical processing units on process characteristics cannot be evaluated due to equipment limitations. The effects of surface cleaning time inside surface cleaning unit are not analyzed.

The utilized PCM equipment is semi-automated equipment, with which the process parameters such as etching time, surface cleaning time, UV exposure time and developing time can be controlled. Different from literature, the effects of phototool pattern geometries on the photochemical machining quality parameters are evaluated for the processing of AISI 304. The effects of processing parameters on dimensional accuracy, which is not common in the literature for AISI 304 stainless steel, are also evaluated.

The purpose of this paper is to study an electrolytic etching method to prepare fine lines on printed circuit board (PCB). And the influence of organics on the side corrosion protection of PCB fine lines during electrolytic etching is studied in detail.

In this paper, the etching factor of PCB fine lines produced by new method and the traditional method was analyzed by the metallographic microscope. In addition, field emission scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) were used to study the inhibition of undercut of the four organometallic corrosion inhibitors with 2,5-dimercapto-1,3,4-thiadiazole, benzotriazole, l-phenylalanine and l-tryptophan in the electrolytic etching process.

The SEM results show that corrosion inhibitors can greatly inhibit undercut of PCB fine lines during electrolytic etching process. XPS results indicate that N and S atoms on corrosion inhibitors can form covalent bonds with copper during electrolytic etching process, which can be adsorbed on sidewall of PCB fine lines to form a dense protective film, thereby inhibiting undercut of PCB fine lines. Quantum chemical calculations show that four corrosion inhibitor molecules tend to be parallel to copper surface and adsorb on copper surface in an optimal form. COMSOL Multiphysics simulation revealed that there is a significant difference in the amount of corrosion inhibitor adsorbed on sidewall of the fine line and the etching area.

As a clean production technology, electrolytic etching method has a good development indicator for the production of high-quality fine lines in PCB industry in the future. And it is of great significance in saving resources and reducing environmental pollution.

High density PCB production requires ever closer investigation of the factors which influence the ability to fabricate efficient circuitry. One of these, etching, is examined, revealing that even that process alone is subject to the effect of physical, chemical and hydraulic parameters. Physical factors include raw materials, circuit geometry and process equipment, etcher spray systems being discussed at length. The implications of the chemical parameters are specifically linked with etchant formulation. Oxidation reduction potential and etchant density effects are also dealt with before the final section on hydraulic factors, where the importance of the design of the hydraulics system is underlined.

Lower manufacturing costs and improved performance are required by the printed circuit board industry. This paper focuses on manufacturing technologies that will permit both technical and cost criteria to be achieved. Existing and emerging fabrication techniques (worldwide) are discussed and a path forward is suggested for cost‐effective manufacture of high‐performance PCBs.

This paper aims to develop an ideal technique for the preparation of print circuit boards (PCBs) with ladder conductive lines on practical industrial process lines.

First, the raw materials of ladder copper-clad laminates were prepared by plating double-sided copper-clad laminates with vertical plating line. Second, etching compensation experiments were designed and conducted to set up the relationships between etching compensation and width of conductive lines on ladder line print circuit boards (LLPCBs). Third, to evaluate the process technique for the preparation of LLPCBs through etching compensation, verification experiments were designed and conducted on a practical industrial process line, and the quality of lines on LLPCBs was observed and evaluated.

Under the judgment of the quality of conductive lines on LLPCBs as well as the feasibility with a practical industrial process line, the process technique for the preparation of LLPCBs with etching compensation is a simple and reliable method which has the potential to be applied in the industry.

It is the first successful report of a new method that produces LLPCBs with etching compensation and has the potential to be applied in the industry.

Early in AT & T Bell Laboratories' involvement with plasma smear removal for multilayer boards, the generic problem of uniform etching over large size panels became obvious. Techniques were developed which provide a quantitative measurement of the etch uniformity. These techniques were used to evaluate the etch performance of existing reactors and as an aid in developing a better understanding of the factors which influence etch uniformity. This characterisation procedure enabled the development of new reactor geometries which greatly improved etch uniformity as compared to previously used configurations. This paper describes these steps along the road to uniform etching of printed circuit boards.

The purpose of this paper is to present the influence of gate dielectric etching on obtained MISFET (metal insulator semiconductor field effect transistor) structures. Because of its properties, aluminum nitride (AlN) layers can be successfully used in a large area of applications. In addition, AIN has a wide bandgap (6.2eV) and high thermal conductivity (3.2 W/cm * K). Its melting temperature is greater than 2,000°C. The relative permittivity is about 9. All these features (especially high power, high temperature and high-frequency) make AlN a useful material in the fields of electronic, optical and acoustic applications.

To fabricate n-channel transistors, silicon technology was used. The 50-nm thick AlN films were deposited using the magnetron sputtering. After preparation of SiO₂/AlN stack as the gate dielectric, the optimization processes of dry etching in plasma environment by Taguchi method were realized. In the next step, three methods of AlN etching were selected and used to MISFET device fabrication. Atomic force microscopy and scanning electron microscopy allowed to surfacing of the state observation after etching process. The current–voltage (I–V) output and transfer characteristics of structures with modified etch technology were measured. Keithley SMU 236/237/238 measurement set was used.

In this research work, a method of AlN etching in a field effect transistor technology was developed and improved. Current−voltage characteristics of obtained MISFET structures were measured and compared. Influence of etching procedure on transistors properties was examined.

The obtained results allow improving the MISFET technology based on AlN film as a gate dielectric. The complete research work will allow using the developed technologies to implement in highly sensitive ion-sensitive field effect transistor (ISFET) structures in the future. The improvement of the etching element in the technology strongly influences the detection capabilities and operating range of the transistor.

The adhesion between electroless copper and a substrate is one of the most important factors in the reliability of thermoplastic printed circuit boards. The purpose of this paper is to investigate the effects of mechanical grinding and acid etching of thermoplastic substrate materials on the adhesion of copper deposited by an electroless copper plating process. The base material of the test substrates was a new high temperature thermoplastic polyphenylene oxide (PPO) compound.

The effects of pre‐treatment on plastic surfaces are analyzed by the following methods: Fourier transform infrared (FTIR), SEM, the Dyne surface energy test and the surface roughness test. The adhesion between electroless copper and thermoplastic substrate is measured with a peel strength test.

The results showed that mechanical grinding of the substrates significantly increased adhesion but the highest adhesion is gained by using an acid etch treatment before electroless plating. These results indicated that adhesion between copper and the substrates was not directly proportional to the roughness and surface energy values.

The conventional sweller/desmear treatment used in a printed circuit board factory for pre‐treating epoxy based laminates prior to electroless plating is not suitable for these PPO compound boards. The copper adhesion is adequate when the substrates are etched with sulphuric acid/chromate solution. In that case the bonding between the metal layer and the plastic surface is stronger than the bondings between the polymer chains of the thermoplastic material. The adhesion mechanism of electroless copper in these mechanically abraded samples is mechanical interlocking of metal particles.

Driven by the demand for higher density in electronic packaging, each signal plane of printed wiring board must accommodate more conductors. As a result, conductor width is becoming narrower each year. This chapter reviews some of the important steps of forming finer line conductors in printed wiring boards, such as surface preparation, plating/etching, photo‐exposure, automatic optical inspection, etc.

The use of fine‐pitch SMD devices has increased the need for accurate and consistent solder paste deposits for reflow soldering. Continued miniaturisation in PCB and SMD lead sizes is presenting the user, paste supplier and print equipment manufacturer with paste printing challenges. Most of these challenges are user‐driven, and are generally met by enhancing associated print equipment and solder paste materials. Recent developments in fine‐particle pastes, water‐soluble and no‐clean pastes are among the improvements in materials. Vision‐assisted stencil aperture and PCB pad alignment, the use of metal squeegees and new stencil fabrication methods are among the latest developments on the equipment side. Printing tests have shown that there is a physical limit for the solder paste printing process, which is defined partly by the nature of the stencil fabrication process, the physical forces and the stencil's ability to meter a precise volume of paste. The challenge as SMD lead sizes decrease is to improve the printing process to match component lead sizes. There is a fear that we are now operating at the very limits of the solder paste printing process. To meet future component developments, there is a need to develop alternative printing processes for solder reflow.